Datasheet

V
N
(mV
RMS
) + 8.5
ǒ
mV
RMS
V
Ǔ
V
OUT
(V)
V
N
(mV
RMS
) + 27
ǒ
mV
RMS
V
Ǔ
V
OUT
(V)
V
N
+ 32mV
RMS
(R
1
) R
2
)
R
2
+ 32mV
RMS
V
OUT
V
REF
TPS73201-Q1
TPS73225-Q1
www.ti.com SGLS303E –MAY 2005–REVISED AUGUST 2013
Output Noise
A precision band-gap reference is used to generate the internal reference voltage, V
REF
. This reference is the
dominant noise source within the TPS732xx and it generates approximately 32 μV
RMS
(10 Hz to 100 kHz) at the
reference output (NR). The regulator control loop gains up the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by:
(1)
Since the value of V
REF
is 1.2 V, this relationship reduces to:
(2)
for the case of no C
NR
.
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, C
NR
, is connected from NR to ground. For C
NR
= 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximate
relationship:
(3)
for C
NR
= 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs C
NR
in the Typical Characteristics section.
The TPS73201 adjustable version does not have the noise-reduction pin available. However, connecting a
feedback capacitor, C
FB
, from the output to the FB pin will reduce output noise and improve load transient
performance.
The TPS732xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above V
OUT
. The charge pump generates ~250 μV of switching noise at ~2 MHz;
however, charge-pump noise contribution is negligible at the output of the regulator for most values of I
OUT
and
C
OUT
.
Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the
PCB be designed with separate ground planes for V
IN
and V
OUT
, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
GND pin of the device.
Internal Current Limit
The TPS732xx internal current limit helps protect the regulator during fault conditions. Foldback helps to protect
the regulator from damage during output short-circuit conditions by reducing current limit when V
OUT
drops below
0.5 V. See Figure 12 in the Typical Characteristics section for a graph of I
OUT
vs V
OUT
.
Shutdown
The Enable pin is active high and is compatible with standard TTL-CMOS levels. V
EN
below 0.5 V (max) turns
the regulator off and drops the ground pin current to approximately 10 nA. When shutdown capability is not
required, the Enable pin can be connected to V
IN
. When a pullup resistor is used, and operation down to 1.8 V is
required, use pullup resistor values below 50 kΩ.
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Product Folder Links: TPS73201-Q1 TPS73225-Q1