Datasheet

TPS732xx
GNDEN FB
IN OUT
V
IN
V
OUT
V
OUT
=
×
1.204
(R
1
+ R
2
)
R
1
C
FB
R
2
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional capacitor
reduces output noise.
R
2
TPS732xx
GNDEN NR
IN OUT
V
IN
V
OUT
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional bypass
capacitor to reduce
output noise.
TPS73201-Q1
TPS73225-Q1
SGLS303E –MAY 2005–REVISED AUGUST 2013 www.ti.com
APPLICATION INFORMATION
The TPS732xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features, combined with low noise and an enable input, make the TPS732xx ideal for portable
applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable
output version. All versions have thermal and over-current protection, including foldback current limit.
Figure 32 shows the basic circuit connections for the fixed voltage models. Figure 33 gives the connections for
the adjustable output version (TPS73201).
Figure 32. Typical Application Circuit for Fixed-Voltage Versions
Figure 33. Typical Application Circuit for
Adjustable-Voltage Versions
R
1
and R
2
can be calculated for any output voltage using the formula shown in Figure 33. Sample resistor values
for common output voltages are shown in Figure 3. For best accuracy, make the parallel combination of R
1
and
R
2
approximately 19 kΩ.
Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-
μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and
improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if
large, fast rise-time load transients are anticipated or the device is located several inches from the power source.
The TPS732xx does not require an output capacitor for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available types and values of capacitors. In applications where
V
IN
– V
OUT
< 0.5 V and multiple low ESR capacitors are in parallel, ringing may occur when the product of C
OUT
and total ESR drops below 50 nF. Total ESR includes all parasitic resistances, including capacitor ESR and
board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance
will meet this requirement.
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