Datasheet
TPS731xx
SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009..........................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS731xx yy yz XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable
(3)
).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted
(1)
PARAMETER TPS731xx UNIT
V
IN
range –0.3 to 6.0 V
V
EN
range –0.3 to 6.0 V
V
OUT
range –0.3 to 5.5 V
V
NR
, V
FB
range –0.3 to 6.0 V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, T
J
–55 to +150 °C
Storage temperature range –65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS
(1)
DERATING FACTOR T
A
≤ 25°C T
A
= 70°C T
A
= 85°C
BOARD PACKAGE R
ΘJC
R
ΘJA
ABOVE T
A
= 25°C POWER RATING POWER RATING POWER RATING
Low-K
(2)
DBV 64°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW
High-K
(3)
DBV 64°C/W 180°C/W 5.6mW/°C 560mW 310mW 225mW
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
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