Datasheet

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1.1 Performance Specification Summary
1.2 Modifications
2 Input/Output Connector Descriptions
Input/Output Connector Descriptions
Table 1 provides a summary of the TPS728185315EVM performance specifications. All specifications are
given for an ambient temperature of 25 ° C.
Table 1. Typical Performance Specification Summary
VOLTAGE RANGE CURRENT RANGE
(V) (mA)
CONDITION
MIN TYP MAX MIN TYP MAX
V
BIAS
IN V
O
= 1.85 V 2.7 6.5
(1)
200
V
IN
IN V
O
= 3.15 V 3.55 6.5
(1)
200
V
OUT
1.795 1.85 1.906 200
(1)
V
OUT
3.056 3.15 3.245 200
(1)
(1)
Linear regulator power dissipation is computed as P
D
= (V
IN
– V
OUT
) × I
OUT
. As specified in the data sheet, the regulator's
package has a finite power dissipation rating depending on the ambient temperature, board type, and airflow. Using V
IN
and/or
V
OUT
voltages other than the typical voltages recommended in the table or using the EVM in an environment with an ambient
temperature higher than 25 ° C significantly reduces the maximum allowed output current. See the data sheet for the regulator
package's thermal resistance data, and see TI application report Digital Designer's Guide to Linear Voltage Regulators and
Thermal Management (SLVA118 ) for a full explanation.
To aid user customization of the EVM, the board was designed with devices having 0603 or larger
footprints. A real implementation likely occupies less total board space.
Changing components can improve or degrade EVM performance. For example, adding a larger output
capacitor reduces output voltage undershoot but lengthens response time after a load transient event.
Adding a larger input capacitor reduces droop at the V
IN
pin that inductive leads from the V
IN
power supply
may cause during a load transient.
J1–VIN Positive connection to the power input supply (V
IN
) for the QFN (DRV) packaged IC.
J2–VOUT Positive connection for the output load on V
OUT
for the QFN (DRV) packaged IC.
J3–GND Return connection for the input supply for both ICs.
J4–GND Ground return connection for the output load for both ICs.
J5–VIN Positive connection to the power input supply (V
IN
) for the chipscale (YZU) packaged IC.
J6–VOUT Positive connection for the output load on V
OUT
for the chipscale (YZU) packaged IC.
JP1– ON/EN/OFF - When this jumper is placed in the ON position, the chipscale (YZU) device's ENable
pin is tied to V
IN
, thereby enabling the device. When the jumper is placed in the OFF position, the the
chipscale (YZU) device's ENable pin is tied to ground, thereby disabling the device.
JP2– VOUT2/VSET/VOUT1 - When this jumper is placed in the VOUT2 position, the QFN (DRV)
packaged device's VSET pin is tied to V
IN
, thereby setting V
OUT
= 3.15 V. When the jumper is placed in
the VOUT1 position, the the QFN (DRV) packaged device's VSET pin is tied to ground, thereby setting
V
OUT
=1.85 V.
JP3– VOUT2/VSET/VOUT1 - When this jumper is placed in the VOUT2 position, the chipscale (YZU)
packaged device's VSET pin is tied to V
IN
, thereby setting V
OUT
= 3.15 V. When the jumper is placed in
the VOUT1 position, the the chipscale (YZU) packaged device's VSET pin is tied to ground, thereby
setting V
OUT
=1.85 V.
JP4– ON/EN/OFF - When this jumper is placed in the ON position, the QFN (DRV) device's ENable pin is
tied to V
IN
, thereby enabling the device. When the jumper is placed in the OFF position, the QFN (DRV)
device's ENable pin is tied to ground, thereby disabling the device.
TP1 – Test point for measuring V
IN
for the QFN (DRV) packaged device.
2 TPS728185315EVM-267 SLVU212 – October 2007
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