Datasheet

TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403H –MAY 2002–REVISED JUNE 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
TPS726xx xyyy z XXX is nominal output voltage (for example, 126 = 1.26V, 15 = 1.5V).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Input voltage, V
I
(2)
–0.3 to 7 V
Voltage range at EN –0.3 to V
I
+ 0.3 V
Voltage on RESET V
IN
+ 0.3 V
Voltage on OUT 6 V
ESD rating, HBM 2 kV
Continuous total power dissipation See Dissipation Rating Table
Operating junction temperature range, T
J
–50 to 150 °C
Maximum junction temperature range, T
J
150 °C
Storage temperature, T
stg
–65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE BOARD R
qJC
R
qJA
DDPAK High K
(1)
2 °C/W 23 °C/W
SOT223 Low K
(2)
15 °C/W 53 °C/W
(1) The JEDEC high K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce
copper traces on top of the board.
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Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625