Datasheet
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1) (2)
POWER DISSIPATION RATINGS
TPS72301
TPS72325
SLVS346B – SEPTEMBER 2003 – REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable.)
TPS723 xxyyz YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com .
(2) Output voltages from –1.2V to –9V in 100mV increments are available. Minimum order quantities apply; contact factory for details and
availability.
Over operating temperature range, unless otherwise noted.
VALUE UNITS
Input voltage range, V
IN
–11 to +0.3 V
Noise reduction pin voltage range, V
NR
–11 to +5.5 V
Enable voltage range, V
EN
–V
IN
to +5.5 V
Output voltage range, V
OUT
–11 to +0.3 V
Output current, I
OUT
Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation, P
D
See Power Dissipation Ratings table
Junction temperature range, T
J
–55 to +150 ° C
Storage temperature range, T
stg
–65 to +150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
T
A
≤ +25 ° c T
A
= +70 ° c T
A
= +85 ° c
DERATING FACTOR POWER POWER POWER
BOARD PACKAGE R
θ JC
R
θ JA
ABOVE T
A
= +25 ° c RATING RATING RATING
Low-K
(1)
DBV 64 ° C/W 255 ° C/W 3.9mW/ ° C 390mW 215mW 155mW
High-K
(2)
DBV 64 ° C/W 180 ° C/W 5.6mW/ ° C 560mW 310mW 225mW
(1) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(2) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
Submit Documentation Feedback