Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- PIN CONFIGURATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- INPUT AND OUTPUT CAPACITOR REQUIREMENTS
- BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE
- INTERNAL CURRENT LIMIT
- INRUSH CURRENT LIMIT
- SHUTDOWN
- DROPOUT VOLTAGE
- TRANSIENT RESPONSE
- UNDERVOLTAGE LOCK-OUT (UVLO)
- MINIMUM LOAD
- OUTPUT REGULATION WITH IN PIN FLOATING
- THERMAL INFORMATION
- POWER DISSIPATION
- PACKAGE MOUNTING

SHUTDOWN MINIMUM LOAD
DROPOUT VOLTAGE
OUTPUT REGULATION WITH IN PIN
TRANSIENT RESPONSE
UNDERVOLTAGE LOCK-OUT (UVLO)
Microcontroller
TPS720xx
TPS62xxx
VIN
EN
SW
FB
IN OUT
BIAS
EN
GND
2.2mF
10mF
10mH
2.5Vto5.5V
Controltoturnon/offthedc/dc
Outputofdc/dcisfloatingwhen
theTPS62xxxENpinislow
GND
TPS720xx
SBVS100D – JUNE 2008 – REVISED AUGUST 2009 ........................................................................................................................................................
www.ti.com
The enable pin (EN) is active high and is compatible The TPS720xx is stable with no output load.
with standard and low voltage, TTL-CMOS levels. Traditional LDOs suffer from low loop gain at very
When shutdown capability is not required, EN can be light output loads. The TPS720xx employs an
connected to the IN pin. innovative, low-current mode circuit under very light
or no-load conditions, resulting in improved output
voltage regulation performance down to zero output
current.
The TPS720xx uses a NMOS pass transistor to
achieve low dropout. When (V
IN
– V
OUT
) is less than
the dropout voltage (V
DO
), the NMOS pass device is
FLOATING
in the linear region of operation and the
input-to-output resistance is the R
DS(ON)
of the NMOS The TPS720xx supports a novel feature in which the
pass element. V
DO
approximately scales with output output of the LDO regulates under light loads when
current because the NMOS device behaves as a the IN pin is left floating. Under normal conditions,
resistor in dropout. when the IN pin is connected to a power source, the
BIAS pin draws only tens of milliamperes. However,
As with any linear regulator, PSRR and transient
when the IN pin is floating, an innovative circuit is
response are degraded as (V
IN
– V
OUT
) approaches
used that allows a mximum current of 500 µ A to be
dropout. This effect is shown in Figure 19 in the
drawn by the load through the BIAS pin, while
Typical Characteristics section.
maintaining the output in regulation. This feature is
particularly useful in power-saving applications where
a dc/dc converter connected to the IN pin is disabled,
but the LDO is required to regulate the output voltage
As with any regulator, increasing the size of the
to a light load.
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
Figure 27 shows an application example where a
microcontroller is not turned off (to maintain the state
of the internal memory), but where the regulated
supply (shown as the TPS62xxx) is turned off to
The TPS720xx uses an undervoltage lock-out circuit
reduce power. In this case, the TPS720xx BIAS pin
on the BIAS pin to keep the output shut off until the
provides sufficient load current to maintain a
internal circuitry is operating properly. The UVLO
regulated voltage to the microcontroller.
circuit has a deglitch feature so that it typically
ignores undershoot transients on the input if they are
less than 50 µ s duration.
Figure 27. Example of Floating IN Pin Regulation
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