Datasheet

Transient Response
Undervoltage Lock-Out (UVLO)
Power Dissipation
Minimum Load
THERMAL INFORMATION
Thermal Protection
P =(V V )xI-
D IN OUT OUT
(1)
Package Mounting
TPS718xx
TPS719xx
www.ti.com ..................................................................................................................................................... SBVS088C – FEBRUARY 2007 – REVISED MAY 2008
As with any linear regulator, PSRR and transient Any tendency to activate the thermal protection circuit
response are degraded as (V
IN
– V
OUT
) approaches indicates excessive power dissipation or an
dropout. This effect is shown in Figure 13 and inadequate heatsink. For reliable operation, junction
Figure 14 in the Typical Characteristics section. temperature should be limited to +125 ° C maximum.
To estimate the margin of safety in a complete design
(including heatsink), increase the ambient
temperature until the thermal protection is triggered;
As with any regulator, increasing the size of the
use worst-case loads and signal conditions. For good
output capacitor will reduce over/undershoot
reliability, thermal protection should trigger at least
magnitude but increase duration of the transient
+35 ° C above the maximum expected ambient
response.
condition of your particular application. This
configuration produces a worst-case junction
temperature of +125 ° C at the highest expected
ambient temperature and worst-case load.
The TPS718xx/TPS719xx utilize an undervoltage
lock-out circuit to keep the output shut off until
The internal protection circuitry of the
internal circuitry is operating properly. The UVLO
TPS718xx/TPS719xx has been designed to protect
circuit has a de-glitch feature so that it typically
against overload conditions. It was not intended to
ignores undershoot transients on the input if they are
replace proper heatsinking. Continuously running the
less than 50 µ s duration. On the TPS719xx, the active
TPS718xx/TPS719xx into thermal shutdown
pulldown discharges V
OUT
when the device is in
degrades device reliability.
UVLO off condition. However, the input voltage needs
to be greater than 0.8V for active pulldown to work.
The ability to remove heat from the die is different for
each package type, presenting different
The TPS718xx/TPS719xx are stable with no output
considerations in the printed circuit board (PCB)
load. Traditional PMOS LDO regulators suffer from
layout. The PCB area around the device that is free
lower loop gain at very light output loads. The
of other components moves the heat from the device
TPS718xx/TPS719xx employ an innovative,
to the ambient air. Performance data for JEDEC low-
low-current mode circuit under very light or no-load
and high-K boards are given in the Dissipation
conditions, resulting in improved output voltage
Ratings table. Using heavier copper increases the
regulation performance down to zero output current.
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation (P
D
) is equal to the
Thermal protection disables the output when the
product of the output current times the voltage drop
junction temperature rises to approximately +160 ° C,
across the output pass element (V
IN
to V
OUT
), as
allowing the device to cool. When the junction
shown in Equation 1 :
temperature cools to approximately +140 ° C the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the Solder pad footprint recommendations for the
regulator, protecting it from damage due to TPS718xx/TPS719xxx are available from the Texas
overheating. Instruments web site at www.ti.com .
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Product Folder Link(s): TPS718xx TPS719xx