Datasheet
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at I
O
= 10 mA, EN = 0 V, C
O
= 4.7 µF/CSR
†
= 1 Ω, SENSE/FB shorted to OUT
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
TPS7101Q, TPS7133Q
TPS7148Q, TPS7150Q
UNIT
J
MIN TYP MAX
Ground current (active mode)
EN ≤ 0.5 V
,
V
I
= V
O
+ 1 V
,
25°C 285 350
µA
Ground
current
(active
mode)
EN
≤
0.5
V,
0 mA ≤ I
O
≤ 500 mA
V
I
V
O
+
1
V,
–40°C to 125°C 460
µ
A
In
p
ut current (standby mode)
EN V
27V≤ V ≤ 10 V
25°C 0.5
µA
Input
current
(standby
mode)
EN
=
V
I
,
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 2
µ
A
Out
p
ut current limit
V
O
=0
V
I
=10V
25°C 1.2 2
A
Output
current
limit
V
O
=
0
,
V
I
=
10
V
–40°C to 125°C 2
A
Pass-element leaka
g
e current in standb
y
EN V
27V≤ V ≤ 10 V
25°C 0.5
µA
gy
mode
EN
=
V
I
,
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 1
µ
A
PG leakage current
Normal o
p
eration
V
PG
=10V
25°C 0.02 0.5
µA
PG
l
ea
k
age curren
t
Normal
operation
,
V
PG
=
10
V
–40°C to 125°C 0.5
µ
A
Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C
Thermal shutdown junction temperature 165 °C
EN logic high (standby mode)
2.5 V ≤ V
I
≤ 6 V
40°Cto125°C
2
V
EN
l
og
i
c
hi
g
h
(
s
t
an
db
y mo
d
e
)
6 V ≤ V
I
≤ 10 V
–
40°C
to
125°C
2.7
V
EN logic low (active mode)
27V≤ V
I
≤ 10 V
25°C 0.5
V
EN
l
og
i
c
l
ow
(
ac
ti
ve mo
d
e
)
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 0.5
V
EN hysteresis voltage 25°C 50 mV
EN input current
0V≤ V
I
≤ 10 V
0V≤ V
I
≤ 10 V
25°C –0.5 0.5
µA
EN
i
npu
t
curren
t
0
V
≤
V
I
≤
10
V
0
V
≤
V
I
≤
10
V
–40°C to 125°C –0.5 0.5
µ
A
Minimum V
I
for active
p
ass element
25°C 2.05 2.5
V
Minimum
V
I
for
active
pass
element
–40°C to 125°C 2.5
V
Minimum V
I
for valid PG
I
PG
= 300 µA
I
PG
= 300 µA
25°C 1.06 1.5
V
Minimum
V
I
for
valid
PG
I
PG
=
300
µ
A
I
PG
=
300
µ
A
–40°C to 125°C 1.9
V
†
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C
O
.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.