Datasheet

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V
OUT1
V
IT
+ V
HYS
V
IT
V
IN
0.6 V
0.0 V
V
OUT2
EN1
EN2
RESET
t
D
t
D
t
D
= Reset Delay
= Undefined State
TPS71319
TPS71334
SBVS055A – DECEMBER 2004 – REVISED JANUARY 2005
output will remain unasserted during transients
shorter than the reset circuit propagation delay (T
P
).
SUPERVISOR DESCRIPTION
Even with a 2.2 µF output capacitor, typical load
The TPS713xx has an on-chip supply voltage super-
transient conditions will not cause RESET to falsely
visor (SVS) that monitors the voltage at OUT2. The
assert.
RESET output will assert if V
OUT2
is below the reset
The RESET pin requires an external resistor to pull
threshold (V
IT
). When OUT2 exceeds the reset
the pin high during the unasserted state. A 10 k Ω to 1
threshold plus hysteresis (V
HYS
), the RESET output
M Ω resistor is suitable for most applications. If the
will remain low for the specified delay time (t
D
). When
resistance is too low, the pin may not pull low enough
OUT2 is disabled by EN2 or the input voltage is
to be recognized as a valid logic signal. If the pull-up
below the under-voltage lockout (UVLO), the reset
resistor is too large, the reset pin leakage may cause
signal is automatically asserted. The functionality of
the device not to pull high enough in the unasserted
the reset circuit is shown in Figure 26 and Table 2 .
state. The pull-up voltage for the RESET pin should
The output accuracy or output divider resistor toler-
not exceed V
IN
+ 0.3 V; doing so will turn on internal
ances have minimal effect on the relative V
IT
ESD protection devices and may damage the device.
threshold accuracy. The reset threshold V
IT
will scale
accordingly to the actual output voltage. The RESET
Figure 26. RESET Timing Diagram
Table 2. Reset Pin Truth Table
UVLO RESET
EN2 Asserted V
OUT2
Asserted
X
(1)
Yes X Yes
Low X X Yes
High No V
OUT2
> V
IT
No
High No V
OUT2
< V
IT
Yes
(1) X = don't care.
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