Datasheet

TPS712xx
GND
EN2 NR
IN OUT1
EN1 OUT2
V
IN
V
OUT1
V
OUT2
0.1
µ
F
2.2
µ
F
2.2
µ
F
0.01
µ
F
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com SBVS049D –MAY 2004–REVISED AUGUST 2010
APPLICATION INFORMATION
1.8 V or less is chosen, the minimum recommended
The TPS712xx family of dual low-dropout (LDO)
output capacitor is 4.7 mF. Any ceramic capacitor that
regulators has been optimized for use in
meets the minimum output capacitor requirements is
noise-sensitive battery-operated equipment. The
suitable. Capacitors with higher ESR may be used,
device features extremely low dropout, high PSRR,
provided the ESR is less than 1Ω.
ultralow output noise, and low quiescent current
(190 mA typical per channel). When both outputs are
OUTPUT NOISE
disabled, the supply currents are reduced to less than
2 mA. A typical application circuit is shown in
The internal voltage reference is a key source of
Figure 24.
noise in an LDO regulator. The TPS712xx has an NR
pin that is connected to the voltage reference through
a 250 kΩ internal resistor. The 250 kΩ internal
resistor, in conjunction with an external ceramic
bypass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. To
achieve a fast startup, the 250 kΩ internal resistor is
shorted for 400 ms after the device is enabled.
Because the primary noise source is the internal
voltage reference, the output noise will be greater for
higher output voltage versions. For the case where
no noise reduction capacitor is used, the typical noise
Figure 24. Typical Application Circuit
(mVrms) over 10 Hz to 100 kHz is 80 times the output
(fixed-voltage versions)
voltage. If a 0.01 mF capacitor is used from the NR
pin to ground, the noise (mVrms) drops to 11.8 times
INPUT AND OUTPUT CAPACITOR
the output voltage. For example, the TPS71256
REQUIREMENTS
exhibits only 33 mVrms of output voltage noise using
a 0.01 mF ceramic bypass capacitor and a 2.2 mF
A 0.1 mF or larger ceramic input bypass capacitor,
ceramic output capacitor.
connected between IN and GND and located close to
the TPS712xx, is required for stability. It improves
STARTUP CHARACTERISITCS
transient response, noise rejection, and ripple
rejection. A higher-value input capacitor may be
To minimize startup overshoot, the TPS712xx will
necessary if large, fast-rise-time load transients are
initially target an output voltage that is approximately
anticipated and the device is located several inches
80% of the final value. To avoid a delayed startup
from the power source.
time, noise reduction capacitors of 0.01 mF or less
are recommended. Larger noise reduction capacitors
The TPS712xx requires an output capacitor
will cause the output to hold at 80% until the voltage
connected between the outputs and GND to stabilize
on the noise reduction capacitor exceeds 80% of the
the internal control loops. The minimum
bandgap voltage. The typical startup time with a
recommended output capacitor is 2.2 mF. If an output
0.001 mF noise reduction capacitor is 60 ms. Once
voltage of
one of the output voltages is present, the startup time
of the other output will not be affected by the noise
reduction capacitor.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257