Datasheet

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Board Layout

Figure 8. TPS709xxEVM-110 Bottom Layer Routing

Figure 9. TPS709xxEVM-110 Schematic

Table 2. TPS709xxEVM-110 Bill of Materials

Count RefDes Value Description Size Part Number MFR

1 C1 2.2 µF Capacitor, ceramic chip, 50 V, X7R, ±10% 1210 STD STD

1 C2 2.2 µF Capacitor, ceramic chip, 6.3 V, X7R, ±10% 0603 STD STD

0 C3 DNP Capacitor, ceramic chip 0603 STD STD

5 J1-5 PEC02SAAN Header, Male 2-pin, 100mil spacing 0.100 in × 2 PEC02SAAN Sullins

1 U1 TPS70933DBV IC, 150 mA, ultra-low IQ, 1-µA LDO regulator with enable SOT-23 TPS709xxDBV TI

1 J3 Shunt, black 100 mil 929950-00 3M

1 – – PCB, 1.20 in × 1.30 in × 0.062 in PWR110 Any

Notes: 1. These assemblies are ESD sensitive, observe ESD precautions.

2. These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.

3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.

4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.

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SLVU689A–June 2011–Revised September 2012 TPS709xxEVM-110 Evaluation Module

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