Datasheet
TPS709
SBVS186E –MARCH 2012–REVISED NOVEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
(1)
PRODUCT V
OUT
XX is the nominal output voltage (for example 28 = 2.8 V).
TPS709xxyyyz YYY is the package designator
Z is the package quantity; R is for reel (3000 pieces), T is for tape (250 pieces)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Specified at T
J
= –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
VALUE
MIN MAX UNIT
V
IN
–0.3 +32 V
Voltage V
EN
–0.3 +7 V
V
OUT
–0.3 +7 V
Maximum output current I
OUT
Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation P
DISS
See the Thermal Information table
Junction, T
J
–55 +150 °C
Temperature
Storage, T
stg
–55 +150 °C
Human body model (HBM) 2 kV
Electrostatic discharge (ESD) ratings
Charged device model (CDM) 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
THERMAL INFORMATION
TPS709xx
DBV DCY DRV
THERMAL METRIC
(1)
UNITS
(SOT-23) (SOT-223) (SON)
5 PINS 4 PINS 6 PINS
θ
JA
Junction-to-ambient thermal resistance 212.1 64.7 73.1
θ
JCtop
Junction-to-case (top) thermal resistance 78.5 47.5 97.0
θ
JB
Junction-to-board thermal resistance 39.5 13.9 42.6
°C/W
ψ
JT
Junction-to-top characterization parameter 2.86 6.8 2.9
ψ
JB
Junction-to-board characterization parameter 38.7 13.8 42.9
θ
JCbot
Junction-to-case (bottom) thermal resistance N/A N/A 12.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated