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V
IN1
V
UVLO
V
UVLO
t
t
t
MR
Input
RESET
Output
120ms
Delay
120ms
Delay
V
RES
Output
Undefined
Output
Undefined
V
RES
NOTEA: V istheminimuminputvoltageforavalid.Thesymbol V isnotcurrentlylistedwithinEIAorJEDEC
standardsforsemiconductorsymbology.
RES RES
RESET
(seeNoteA)
V
PG
t
t
t
PG1Output
V
IT+
(seeNoteB)
V
IN1
V
OUT1
V
PG1
V
(seeNoteB)
V
UVLO
V
UVLO
PG1
Threshold
Voltage
Output
Undefined
Output
Undefined
NOTESA:V istheminimuminputvoltageforavalidPG.Thesymbol V isnotcurrentlylistedwithinEIAorJEDEC
standardsforsemiconductorsymbology.
B:
PG1 PG1
V tripvoltageistypically5%lowerthantheoutputvoltage(95%V ).V toV isthehysteresisvoltage.
IT IT- -
O IT+
NOTES
(seeNoteA)
IT-
TPS70845, TPS70848
TPS70851, TPS70858
TPS70802
SLVS301D – JUNE 2000 – REVISED DECEMBER 2007
RESET Timing Diagram
PG1 Timing Diagram
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