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V
OUT2
V
IN1
V
IN2
V
OUT1
V
SENSE1
PG1
PG2
V
SENSE2
V
OUT2
V
IN
V
OUT1
PG2
>2V
<0.7V
>2V
<0.7V
TPS708xxPWP
(FixedOutputOption)
0.1 Fm
0.1 Fm
10 Fm
250kW
250kW
10 Fm
EN1
EN1
EN2
EN2
RESET
RESET
MR
95%
95%
FAULTONV
OUT1
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO
MR
120ms
t
1
MR
(PG1tiedto )MR
V
OUT2
V
OUT1
RESET
PG1
PG2
EN1
EN2
TPS70845, TPS70848
TPS70851, TPS70858
TPS70802
SLVS301D – JUNE 2000 – REVISED DECEMBER 2007
Application condition: V
IN1
and V
IN2
are tied to
same fixed input voltage greater than V
UVLO
. PG1 is
tied to MR.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 (tied to MR) and PG2 are
at logic low. Since MR is at logic low, RESET is also
at logic low. When EN2 is taken to logic low, V
OUT2
turns on. Later, when EN1 is taken to logic low, V
OUT1
turns on. When V
OUT2
reaches 95% of its regulated
output voltage, PG2 goes to logic high. When V
OUT1
reaches 95% of its regulated output voltage, PG1
goes to logic high. When V
IN1
is greater than V
UVLO
and MR (tied to PG2) is at logic high, RESET is
pulled to logic high after a 120-ms delay. When a
fault on V
OUT1
causes it to fall below 95% of its
regulated output voltage, PG1 (tied to MR) goes to
logic low. Since MR is logic low, RESET goes to logic
low. V
OUT2
is unaffected.
Figure 36. Timing When There is a Fault on V
OUT1
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