Datasheet

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TPS70851PWP
5V
0.1 Fm
0.1 Fm
10 Fm
10 Fm
EN1
MR
MR
RESET
EN1
EN2
EN2
<0.7V
>2V
<0.7V
>2V
<0.7V
>2V
V
OUT1
V
IN1
V
SENSE1
V
SENSE2
V
OUT2
V
IN2
PG1
PG1
PG2
PG2
250kW
250kW
250kW
1.8V
3.3V
RESET
Core
I/O
DESCRIPTION (CONTINUED)
TPS70845, TPS70848
TPS70851, TPS70858
TPS70802
SLVS301D – JUNE 2000 – REVISED DECEMBER 2007
The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have
extremely low noise output performance without using any added filter bypass capacitors and are designed to
have a fast transient response and be stable with 10- µ F low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.
Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow
the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on
regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a
voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µ A
over the full range of output current and full range of temperature). This LDO family also features a sleep mode;
applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high
signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2
µ A at T
J
= +25 ° C.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage condition at V
OUT1
. The PG1 pin can be used to implement a SVS ( RESET,
POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at
V
OUT2
. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.
The TPS708xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of
an undervoltage condition. RESET also indicates the status of the manual reset pin ( MR). When MR is in the
logic high state, RESET goes to a high impedance state after a 120-ms delay. To monitor V
OUT1
, the PG1 output
pin can be connected to MR. To monitor V
OUT2
, the PG2 output pin can be connected to MR.
The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until
V
IN1
reaches 2.5V.
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