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UVLO
Comp
+
-
+
-
+
-
+
-
Thermal
Shutdown
2.5V
+-
Current
Sense
Reference
V
ref
V
ref
ENA_1
ENA_1
FallingEdge
Delay
0.95xV
ref
FB1
0.95xV
ref
FB2
RisingEdge
Deglitch
Current
Sense
+-
ENA_2
ENA_2
V
ref
V
IN1
(2Pins)
GND
EN
V
IN2
(2Pins)
SEQ
(seeNoteB)
FB1
(seeNoteA)
PG1
MR2
RESET
FB2
(seeNoteA)
V
IN1
MR1
V
IN1
PG
Comp
RisingEdge
Deglitch
Reset
Comp
V
OUT1
(2Pins)
V
OUT2
(2Pins)
+
-
FallingEdge
Deglitch
0.83 x V
ref
FB2
V UVComp
OUT2
FallingEdge
Deglitch
0.83 x V
ref
FB1
V UVComp
OUT1
Power
Sequence
Logic
ENA_1
ENA_2
V
IN1
TPS70745, TPS70748
TPS70751, TPS70758
TPS70702
SLVS291D – MAY 2000 – REVISED DECEMBER 2007
Adjustable Voltage Version
A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the
device. For other implementations, refer to FB terminals connection discussion in the Application Information
section.
B. If the SEQ terminal is floating at the input, V
OUT2
powers up first
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