Datasheet

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Split Voltage DSP Application
1.8 V
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
TPS70751PWP
5 V
3.3 V
I/O
MR1
Core
0.1 mF
RESET
10 mF
10 mF
0.1 mF
DSP
MR2
PG1
EN
250 kW
>2 V
<0.7 V
250 kW
>2 V
<0.7 V
>2 V
<0.7 V
5 V
83%
95%
120ms
EN
V
OUT2
(Core)
PG1
RESET
SEQ
95%
83%
V
OUT1
(I/O)
NOTE A: t1 − Time at which both V
OUT1
and V
OUT2
are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70745, TPS70748
TPS70751, TPS70758
TPS70702
SLVS291D – MAY 2000 – REVISED DECEMBER 2007
Figure 41 shows a typical application where the TPS70751 is powering up a DSP. In this application, by
grounding the SEQ pin, V
OUT1
(I/O) is powered up first, and then V
OUT2
(core).
Figure 41. Application Timing Diagram (SEQ = Low)
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