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RESET
V
OUT2
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
V
I
V
OUT1
MR1
0.1 mF
10 mF
10 mF
0.1 mF
MR2
EN
TPS707xxPWP
(FixedOutputOption)
>2 V
<0.7 V
83%
95%
83%
95%
120ms
ENABLE
V
OUT2
V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQUENCE
NOTE A: t1 − Time at which both V
OUT1
and V
OUT2
are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
V
OUT2
faults out
TPS70745, TPS70748
TPS70751, TPS70758
TPS70702
SLVS291D – MAY 2000 – REVISED DECEMBER 2007
Application condition: V
IN1
and V
IN2
are tied to the
same fixed input voltage greater than the V
UVLO
; SEQ
is tied to logic high; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
EN is initially high; therefore, both regulators are off
and PG1 and RESET are at logic low. With SEQ at
logic high, when EN is taken low, V
OUT2
turns on.
V
OUT1
turns on after V
OUT2
reaches 83% of its
regulated output voltage. When V
OUT1
reaches 95%
of its regulated output voltage, PG1 (tied to MR2)
goes to logic high. When both V
OUT1
and V
OUT2
reach
95% of their respective regulated output voltages and
both MR1 and MR2 (tied to PG1) are at logic high,
RESET is pulled to logic high after a 120ms delay.
When a fault on V
OUT2
causes it to fall below 95% of
its regulated output voltage, RESET returns to logic
low and V
OUT1
begins to power down because SEQ is
high. When V
OUT1
falls below 95% of its regulated
output voltage, PG1 (tied to MR2) returns to logic low.
Figure 40. Timing when V
OUT2
Faults Out
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