Datasheet

2V
0.7V
TPS704xxPWP
(FixedOutputOption)
22 Fm
0.22 Fm
0.22 Fm
250kW
250kW
250kW
47 Fm
EN1
EN2
>2V
<0.7V
>2V
<0.7V
EN2
EN1
V
IN2
V
IN1
V
IN
V
OUT2
V
SENSE2
MR
PG2
RESET
V
SENSE1
V
OUT1
MR
RESET
PG2
V
OUT2
V
OUT1
95%
95%
EN2
EN1
V
OUT1
V
OUT2
PG2
PG1
MR
RESET
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO
MR
120ms
t
1
TPS70445, TPS70448
TPS70451, TPS70458
TPS70402
SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010 www.ti.com
Application condition: V
IN1
and V
IN2
are tied to the
same fixed input voltage greater than V
UVLO
. MR is
initially logic high but is eventually toggled.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 are at logic low.
Since V
IN1
is greater than V
UVLO
and MR is at logic
high, RESET is also at logic high. When EN2 is taken
to logic low, V
OUT2
turns on. Later, when EN1 is taken
to logic low, V
OUT1
turns on. When V
OUT2
reaches
95% of its regulated output voltage, PG2 goes to
logic high. When V
OUT1
reaches 95% of its regulated
output voltage, PG1 goes to logic high. When MR is
taken to logic low, RESET is taken low. When MR
returns to logic high, RESET returns to logic high
after a 120-ms delay.
Figure 39. Timing When MR is Toggled
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