Datasheet

>2V
<0.7V
>2V
<0.7V
TPS704xxPWP
(FixedOutputOption)
0.22 Fm
0.22 Fm
47 Fm
22 Fm
250kW
250kW
RESET
RESET
V
IN
V
IN1
V
IN2
V
OUT1
V
SENSE1
PG1
MR
MR
V
OUT1
EN1
EN2
EN1
EN2
V
SENSE2
V
OUT2
PG2
PG2
V
OUT2
95%
95%
PG2
PG1
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO
MR
120ms
t
1
EN2
EN1
V
OUT2
V
OUT1
MR
MR(PG2tiedto )
RESET
TPS70445, TPS70448
TPS70451, TPS70458
TPS70402
www.ti.com SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010
APPLICATION INFORMATION
Sequencing Timing Diagrams
This section provides a number of timing diagrams
showing how this device functions in different
configurations.
Application condition: V
IN1
and V
IN2
are tied to the
same fixed input voltage greater than V
UVLO
. PG2 is
tied to MR.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 (tied to MR) are
at logic low. Since MR is at logic low, RESET is also
at logic low. When EN1 is taken to logic low, V
OUT1
turns on. Later, when EN2 is taken to logic low, V
OUT2
turns on. When V
OUT1
reaches 95% of its regulated
output voltage, PG1 goes to logic high. When V
OUT2
reaches 95% of its regulated output voltage, PG2
(tied to MR) goes to logic high. When V
IN1
is greater
than V
UVLO
and M R (tied to PG2) is at logic high,
RESET is pulled to logic high after a 120-ms delay.
When EN1 and EN2 are returned to logic high, both
devices power down and both PG1, PG2 (tied to
MR2), and RESET return to logic low.
Figure 38. Timing When V
OUT1
Is Enabled Before V
OUT2
Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 27