Datasheet

TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

www.ti.com

The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have

extremely low noise output performance without using any added filter bypass capacitors and are designed to

have a fast transient response and be stable with 47-mF low ESR capacitors.

These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.

Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the

designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on

regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a

voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 mA

over the full range of output current and full range of temperature). This LDO family also features a sleep mode;

applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high

signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2

mA at T

= +25°C.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator

is turned off (disabled).

The PG1 pin reports the voltage condition at V

OUT1

. The PG1 pin can be used to implement a SVS (RESET,

POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at

OUT2

. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.

The TPS704xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output

and requires a pull-up resistor for normal operation. When pulled up, RESET goes into a high impedance state

(that is, logic high) after a 120-ms delay when both of the following conditions are met. First, V

IN1

must be above

the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor

OUT1

, the PG1 output pin can be connected to MR. To monitor V

OUT2

, the PG2 output pin can be connected to

MR. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be left

floating.

Internal bias voltages are powered by V

IN1

and require 2.7 V for full functionality. Each regulator input has an

undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.