Datasheet

UVLO1
Comp
+
-
+
-
+
-
-
+
+
-
Thermal
Shutdown
2.5V
+-
Current
Sense
Reference
V
ref
V
ref
ENA_1
FB1
ENA_1
120ms
Delay
0.95xVref
FB1
0.95xV
ref
FB2
RisingEdge
Deglitch
Current
Sense
+-
ENA_2
ENA_2
V
ref
V
IN1
(2Pins)
GND
EN
V
IN2
(2Pins)
SEQ
(seeNoteB)
PG1
MR2
RESET
V
IN1
MR1
V
IN1
PG
Comp
RisingEdge
Deglitch
Reset
Comp
V
OUT2
(2Pins)
+
-
FallingEdge
Deglitch
0.83 x V
ref
FB2
V UVComp
OUT2
FallingEdge
Deglitch
0.83 x V
ref
FB1
V UVComp
OUT1
Power
Sequence
Logic
ENA_1
ENA_2
V
IN1
2.5V
UVLO2
Comp
10kW
V
SENSE1
(seeNoteA)
V (2Pins)
OUT1
V
SENSE2
(seeNoteA)
10kW
TPS70345, TPS70348
TPS70351, TPS70358
TPS70302
www.ti.com SLVS285H –AUGUST 2000–REVISED APRIL 2010
Fixed Voltage Version
A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other
implementations, refer to FB terminals connection discussion in the Application Information section.
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