Datasheet

1.8V
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
TPS70351PWP
5V
3.3V
I/O
MR1
Core
0.22 Fm
RESET
22 Fm
47 Fm
0.22 Fm
DSP
MR2
PG1
EN
250kW
>2V
<0.7V
250kW
>2V
<0.7V
>2V
<0.7V
V
OUT2
TPS70345, TPS70348
TPS70351, TPS70358
TPS70302
SLVS285H –AUGUST 2000–REVISED APRIL 2010 www.ti.com
The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up
sequence control, designed primarily for DSP applications. These devices have low noise output performance
without using any added filter bypass capacitors, and are designed to have a fast transient response and be
stable with 47 mF low ESR capacitors.
These devices have fixed 3.3 V/2.5 V, 3.3 V/1.8 V, 3.3 V/1.5 V, 3.3 V/1.2 V, and adjustable voltage options.
Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the
designer to configure the source power.
Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically
160mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass
element is a voltage-driven device, the quiescent current is very low and independent of output loading
(maximum of 250 mA over the full range of output current). This LDO family also features a sleep mode; applying
a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 mA at T
J
= +25°C.
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two
regulators are sensed at the V
SENSE1
and V
SENSE2
pins respectively.
The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is
enabled and the SEQ terminal is pulled high or left open, V
OUT2
turns on first and V
OUT1
remains off until V
OUT2
reaches approximately 83% of its regulated output voltage. At that time V
OUT1
is turned on. If V
OUT2
is pulled
below 83% (that is, in an overload condition) of its regulated voltage, V
OUT1
is turned off. Pulling the SEQ
terminal low reverses the power-up order and V
OUT1
is turned on first. The SEQ pin is connected to an internal
pull-up current source.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage condition at V
OUT1
. The PG1 pin can be used to implement an SVS (POR, or
power-on reset) for the circuitry supplied by regulator 1.
The TPS703xx features a RESET (SVS, POR, or power-on reset). RESET is an active low, open drain output
and requires a pull-up resistor for normal operation. When pulled up, RESET goes to a high impedance state
(that is, logic high) after a 120 ms delay when all three of the following conditions are met. First, V
IN1
must be
above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third,
V
OUT2
must be above approximately 95% of its regulated voltage. To monitor V
OUT1
, the PG1 output pin can be
connected to MR1 or MR2. RESET can be used to drive power-on reset or a low-battery indicator. If RESET is
not used, it can be left floating.
Internal bias voltages are powered by V
IN1
and require 2.7V for full functionality. Each regulator input has an
undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.
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