Datasheet

NOTES: A.V istheminimuminputvoltageforavalid .ThesymbolV isnotcurrentlylistedwithinEIAorJEDEC
RES RES
RESET
standards forsemiconductorsymbology.
B. V tripvoltageistypically5%lowerthantheoutputvoltage(95%V ). toV i
IT-
O IT+
V
IT-
sthehysteresisvoltage.
Output
Undefined
Output
Undefined
V
IN2
V
RES
(seeNoteA)
V
RES
t
t
t
V
OUT2
Threshold
Voltage
RESET
Output
120ms
Delay
120ms
Delay
V
IT+
(seeNoteB)
V
IT-
(seeNoteB)
V
IT+
(seeNoteB)
V
IT-
(seeNoteB)
NOTES: A. V istheminimuminputvoltageforavalidPG1.ThesymbolV isnotcurrentlylistedwithinEIAorJEDEC
PG1 PG1
standards forsemiconductorsymbology.
B. V tripvoltageistypically5%lowerthantheoutputvoltage(95%V ). toV i
IT-
O IT+
V
IT-
sthehysteresisvoltage.
V
PG1
t
t
t
Threshold
Voltage
PG1
Output
V
IT+
(see NoteB)V
IT+
(seeNoteB)
V
IN1
V
OUT2
V
PG1
(seeNoteA)
V
IT-
(seeNoteB)
V
IT-
(seeNoteB)
V
UVLO
V
UVLO
Output
Undefined
Output
Undefined
TPS70345, TPS70348
TPS70351, TPS70358
TPS70302
SLVS285H –AUGUST 2000–REVISED APRIL 2010 www.ti.com
RESET Timing Diagram
with V
IN1
Powered Up, MR1 and MR2 at Logic High
PG1 Timing Diagram
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