Datasheet

Test Results
4-6
Test Results
In Figure 4–9, V
OUT2
is pulsed into a shorted condition. Because SEQUENCE
is high, V
OUT1
is disabled after the internal current limit circuitry disables
V
OUT2
. PG1 (CH3), which is tied to MR1, goes low when V
OUT1
falls below
95% of its regulated voltage. RESET
(CH4) goes low when V
OUT2
falls below
95% of its regulated voltage.
Figure 4–9. Timing When SEQUENCE Is High, With a Fault on V
OUT2
V
IN1
= 4.3 V
V
IN2
= 2.8 V
V
OUT1
(CH1) = 1 mA load
V
OUT2
(CH2) = no load to a
shorted condition
In Figure 4–10, MR (CH3) is toggled low and RESET (CH4) follows MR1.
V
OUT1
(CH1) and V
OUT2
(CH2) are unaffected.
Figure 4–10. Timing When MR Is Toggled
V
IN1
= 4.3 V
V
IN2
= 2.8 V
V
OUT1
(CH1) = 1 mA load
V
OUT2
(CH2) = no load