Datasheet

Test Results
4-5
Test Results
In Figure 4–7, V
OUT1
(CH1) is pulsed into a shorted condition. Because
SEQUENCE is high, V
OUT2
(CH2) is not disabled after the internal current limit
circuitry disables V
OUT1
. PG1 (CH3), which is tied to MR1, goes low when
V
OUT1
falls below 95% of its regulated voltage. RESET (CH4) follows MR1.
Figure 4–7. Timing When SEQUENCE Is High, With a Fault on V
OUT1
V
IN1
= 4.3 V
V
IN2
= 2.8 V
V
OUT1
(CH1) = no load to a
shorted condition
V
OUT2
(CH2) = 1 mA load
In Figure 4–8, V
OUT2
(CH2) is pulsed into a shorted condition. Because
SEQUENCE is low, V
OUT1
(CH1) is not disabled after the internal current limit
circuitry disables V
OUT2
. PG1 (CH3), which is tied to MR1, stays high. RESET
(CH4) goes low when V
OUT2
falls below 95% of its regulated voltage.
Figure 4–8. Timing When SEQUENCE Is Low, With a Fault on V
OUT2
V
IN1
= 4.3 V
V
IN2
= 2.8 V
V
OUT1
(CH1) = 1 mA load
V
OUT2
(CH2) = no load to a
shorted condition