TPS70351EVM LowĆDropout, DualĆOutput Linear Regulator EVM For Using the TPS70351 User’s Guide October 2000 POWER MANAGEMENT PRODUCTS SLVU036
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Preface About This Manual This user’s guide describes the TPS70351EVM low-dropout, dual-output evaluation module (SLVP165). The SLVP165 provides a convenient method for evaluating the performance of a dual-output linear regulator. How to Use This Manual - Chapter 1 Introduction Chapter 2 EVM Adjustments and Test Points Chapter 3 Circuit Design Chapter 4 Test Results Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement.
Related Documentation From Texas Instruments Related Documentation From Texas Instruments - TPS70351 data sheets (literature number SLVS285) Trademarks PowerPAD is a trademark of Texas Instruments.
Running Title—Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Low Dropout Voltage Linear Regulator Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Title—Attribute Reference Figures 1–1 1–2 1–3 1–4 1–5 2–1 3–1 3–2 3–3 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 Typical LDO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLVP165B EVM Universal LDO Tester Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction This user’s guide describes the TPS70351EVM165 low-dropout, dual-output evaluation module (SLVP165B). LDOs provide ideal power supplies for rapidly transitioning DSP loads. The TPS703xx family of devices is designed to provide a complete power management solution for DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required.
Low Dropout Voltage Linear Regulator Circuit Operation 1.1 Low Dropout Voltage Linear Regulator Circuit Operation In TI’s low dropout voltage linear regulator topology, a PMOS transistor is used for the pass element. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading.
Design Strategy 1.2 Design Strategy The TI SLVP165B EVM provides a convenient method for evaluating the performance of TPS703xx dual-output linear regulators. The EVM provides proven, demonstrated reference designs and test modes to aid in evaluation. The board contains a power supply along with an onboard transient generator. The transient slew rate can be modified by changing two resistors. Jumpers allow settings of minimum/maximum load as well as device-enabling and power sequencing.
VIN1 VIN2 3 4 2 1 R2 10 kΩ R1 4.3 kΩ C1 1µF GND GND J1 C2 100 µ F ENABLE On DL4148 D1 1 2 R3 5.1 k Ω J2 C3 100 µ F GND VCC + + Off S1 6 THRES 2 TRIG CTL OUT U1 TLC555D 1 GND Sense C4 0.1 µ F VCC 4 RESET 7 DISCH 8 C6 0.1 µ F C5 0.1 µ F 5 3 PGD GND C7 0.1 µ F TP18 TP2 VIN2 Sense JP2 JP1 4 2 3 1 R4 10 kΩ 2IN 2OUT 1OUT 1IN VCC REG GND VDD U2 TPS2812 JP3 TP1 VIN1 5 7 8 6 TP3 TP5 TP4 TP7 TP9 R8 R7 R6 R5 C9 0.
Bill of Materials 1.4 Bill of Materials Table 1–2 lists materials required for the SLVP165 EVM. Table 1–2. SLVP165B EVM Bill of Materials Ref Des Qty Part Number Description MFG Size C1 1 ECJ-2VF1C105Z Capacitor, ceramic, 1.0 uF, 16 V, 80% – 20%, Y5V Panasonic 805 C2 – 3 2 TPSD107M010R100 Capacitor, tantalum, 100 µF, 10 V, 100-mΩ, 20% AVX D Size C4 – 7, 9, 7 14, 15 GRM39X7R104K016A Capacitor, ceramic, 0.
Bill of Materials Table 1–2. SLVP165B EVM Bill of Materials (Continued) Ref Des Qty Part Number Description MFG Size R15 – 19 R15A – 19A 10 ERJ–1WYJ33OU Resistor, chip, 33 Ω, 1 W, 5% Panasonic 2512 R20 – 24 R20A – 24A 10 ERJ–1WY100U Resistor, chip, 10 Ω, 1 W, 5% Panasonic 2512 S1 1 EG1218 Switch, 1P2T, slide, PC-mount, 200 mA E–Switch TP1, 2, 16, 17 4 131–4244–00 Adaptor, 3.
Board Layout 1.5 Board Layout Figures 1–3 through 1-5 show the board layout for the SLVP165B EVM. Figure 1–3. Top Layer Top Layer Figure 1–4.
Board Layout Figure 1–5.
Chapter 2 EVM Adjustments and Test Points This chapter explains the following EVM adjustment modes: - Adjustment by switch and jumper Adjustment through changing components Figure 2–1 shows the locations of the adjustment points on the board. Topic Page 2.1 Adjustment by Switch and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2.2 Adjustment Through Component Changes . . . . . . . . . . . . . . . . . . . . . . 2–3 2.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . .
Adjustment by Switch and Jumpers 2.1 Adjustment by Switch and Jumpers S1 switches the transient generator on or off. Table 2–1 lists adjustments that can be made by jumpers. Table 2–1. Jumper Functions Jumper Setting Functional Description JP1 Short 1-2 – MR2 tied to GND RESET follows MR2 Short 2-3 – MR2 tied to PG_1 RESET will go high after a 120 ms delay when VOUT2 reaches 95% of its regulated voltage and when PG_1 goes high due to VOUT1 reaching 95% of its regulated voltage.
Adjustment Through Component Changes 2.2 Adjustment Through Component Changes Through minor soldering work, the onboard device can be changed to any of the fixed-voltage members of the TPS703xx LDO family. In addition, Table 2–2 summarizes the most common components which a user might wish to replace in order to more fully characterize the LDO. Table 2–2.
Test Setup 5) Verify that the output voltage (measured at the VOUT1 and VOUT2 pins respectively) has the desired value. 6) Table 2–4 shows the three recommended options for loading each regulator. Table 2–4.
Chapter 3 Circuit Design This chapter describes the LDO circuit design procedure. Topic 3.1 Page ESR and Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESR and Transient Response 3.1 ESR and Transient Response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These impedances are resistive as well as inductive.
ESR and Transient Response When Co is conducting current to the load, initial voltage at the load will be VO = V(Co) – VESR. Due to the discharge of Co, the output voltage VO will drop continuously until the response time t1 of the LDO is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 3–3. The figure also shows the impact of different ESRs on the output voltage.
3-4 Circuit Design
Chapter 4 Test Results This chapter presents laboratory test results for the TPS70351 LDO design. Topic 4.1 Page Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Results 4.1 Test Results Figures 4–1 through 4–10 show the results of various test conditions using the TPS70351 device. In Figure 4–1, the onboard transient generator is used to pulse IOUT1 (CH1) on VOUT1 (CH2–AC) from 1 mA to 1 A. A current loop was added to the board to measure the load current. Figure 4–1. VOUT1 Load Transient VIN1 = 4.3 V VIN2 = 2.
Test Results In Figure 4-3, ENABLE (CH1) is pulsed. When SEQ is high, VOUT1 (CH2) powers up after VOUT2 (CH3) reaches 85% of its regulated output. PG1 (CH4), which is tied to MR1, goes high when VOUT1 reaches 95% of its regulated voltage. Figure 4–3. Timing When SEQUENCE Is High VIN1 = 4.3 V VIN2 = 2.8 V IOUT1 = 0.6 A IOUT2 = 1.1 A In Figure 4-3, ENABLE (CH1) is pulsed. When SEQ is low, VOUT2 (CH3) powers up after VOUT1 (CH2) reaches 85% of its regulated output.
Test Results In Figure 4–5, ENABLE (CH1) is pulsed. SEQUENCE can be either low or high. With PG1 tied to MR1, RESET (CH4) goes high 120 ms after both VOUT1 and VOUT2 have reached 95% of their respective regulated output voltages. Figure 4–5. Timing Including RESET VIN1 = 4.3 V VIN2 = 2.8 V IOUT1 = 0.6 A IOUT2 = 1.1 A In Figure 4–6, VOUT1 (CH1) is pulsed into a shorted condition. Because SEQUENCE is low, VOUT2 (CH2) is disabled after the internal current limit circuitry disables VOUT1.
Test Results In Figure 4–7, VOUT1 (CH1) is pulsed into a shorted condition. Because SEQUENCE is high, VOUT2 (CH2) is not disabled after the internal current limit circuitry disables VOUT1. PG1 (CH3), which is tied to MR1, goes low when VOUT1 falls below 95% of its regulated voltage. RESET (CH4) follows MR1. Figure 4–7. Timing When SEQUENCE Is High, With a Fault on VOUT1 VIN1 = 4.3 V VIN2 = 2.
Test Results In Figure 4–9, VOUT2 is pulsed into a shorted condition. Because SEQUENCE is high, VOUT1 is disabled after the internal current limit circuitry disables VOUT2. PG1 (CH3), which is tied to MR1, goes low when VOUT1 falls below 95% of its regulated voltage. RESET (CH4) goes low when VOUT2 falls below 95% of its regulated voltage. Figure 4–9. Timing When SEQUENCE Is High, With a Fault on VOUT2 VIN1 = 4.3 V VIN2 = 2.
