Datasheet

RESET
V
OUT2
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
V
I
V
OUT1
MR1
0.22 Fm
22 Fm
47 Fm
0.22 Fm
MR2
EN
TPS703xxPWP
(FixedOutputOption)
>2V
<0.7V
250kW
V
IN
120ms
EN
V
OUT2
V
OUT1
PG1
MR1
MR2
(MR2 tiedtoPG1)
RESET
SEQUENCE
95%
83%
83%
95%
t
1
(see NoteA)
FaultonV
OUT1
NOTEA:t :TimeatwhichbothV andV aregreaterthanthePGthresholdsand islogichigh.
1 OUT1 OUT2
MR1
TPS70345, TPS70348
TPS70351, TPS70358
TPS70302
SLVS285H –AUGUST 2000–REVISED APRIL 2010 www.ti.com
Application conditions not shown in block
diagram:
V
IN1
and V
IN2
are tied to the same fixed input
voltage greater than V
UVLO
; SEQ is tied to logic
high; PG1 is tied to MR2; MR1 is not used and is
connected to V
IN
.
Explanation of timing diagrams:
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic high, when EN is taken low, V
OUT2
turns on. V
OUT1
turns on after V
OUT2
reaches 83%
of its regulated output voltage. When V
OUT1
reaches 95% of its regulated output voltage, PG1
(tied to MR2) goes to logic high. When both
V
OUT1
and V
OUT2
reach 95% of their respective
regulated output voltages and both MR1 and
MR2 (tied to PG1) are at logic high, RESET is
pulled to logic high after a 120 ms delay. When a
fault on V
OUT1
causes it to fall below 95% of its
regulated output voltage, PG1 (tied to MR2) goes
to logic low.
Figure 41. Timing When a Fault Occurs on V
OUT1
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