Datasheet

LDO
V
in
V
ESR
I
out
R
ESR
C
out
R
LOAD
V
out
+
−
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009 www.ti.com
Figure 38 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
Figure 38. LDO Output Stage with Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V
(CO)
= V
OUT
). This condition means no current is flowing into the
C
OUT
branch. If I
OUT
suddenly increases (a transient condition), the following results occur:
• The LDO is not able to supply the sudden current need because of its response time (t
1
in Figure 39).
Therefore, capacitor C
OUT
provides the current for the new load condition (dashed arrow). C
OUT
now acts like
a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop
occurs at R
ESR
. This voltage is shown as V
ESR
in Figure 38.
• When C
OUT
is conducting current to the load, initial voltage at the load will be V
OUT
= V
(CO)
– V
ESR
. As a result
of the discharge of C
OUT
, the output voltage V
OUT
drops continuously until the response time t
1
of the LDO is
reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until
it reaches the regulated voltage. This period is shown as t
2
in Figure 39.
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