Datasheet

MR
V
OUT2
V
IN1
V
IN2
EN1
EN2
V
OUT1
V
SENSE1
PG1
RESET
PG2
MR
V
SENSE2
V
OUT2
V
IN
V
OUT1
PG2
0.1 Fm
RESET
10 mF
10 mF
0.1 mF
EN1
2V
0.7V
TPS702xxPWP
(FixedOutputOption)
>2V
<0.7V
EN2
250kW
250kW
250kW
>2V
<0.7V
95%
95%
EN2
V
OUT2
V
OUT1
PG2
PG1
EN1
MR
RESET
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO
MR
120ms
t
1
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com SLVS286E –JUNE 2000–REVISED DECEMBER 2009
Application condition: V
IN1
and V
IN2
are tied to the
same fixed input voltage greater than V
UVLO
. MR is
initially logic high but is eventually toggled.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 are at logic low.
Since V
IN1
is greater than V
UVLO
and MR is at logic
high, RESET is also at logic high. When EN2 is taken
to logic low, V
OUT2
turns on. Later, when EN1 is taken
to logic low, V
OUT1
turns on. When V
OUT2
reaches
95% of its regulated output voltage, PG2 goes to
logic high. When V
OUT1
reaches 95% of its regulated
output voltage, PG1 goes to logic high. When MR is
taken to logic low, RESET is taken low. When MR
returns to logic high, RESET returns to logic high
after a 120ms delay.
Figure 35. Timing When MR is Toggled
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