Datasheet

V
OUT2
V
IN1
V
IN2
EN
1
EN2
V
OUT1
V
SENSE1
PG1
MR
RESET
PG2
V
SENSE2
V
OUT2
TPS702xxPWP
(FixedOutputOption)
V
IN
V
OUT1
PG2
0.1 Fm
RESET
10 Fm
10 Fm
0.1 Fm
MR
EN1
>2V
<0.7V
EN2
250kW
250kW
>2V
<0.7V
95%
95%
EN2
V
OUT2
V
OUT1
PG2
PG1
EN1
MR
(PG1tiedto )MR
120ms
t
1
RESET
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO
MR
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009 www.ti.com
APPLICATION INFORMATION
Sequencing Timing Diagrams
This section provides a number of timing diagrams
showing how this device functions in different
configurations.
Application condition: V
IN1
and V
IN2
are tied to the
same fixed input voltage greater than V
UVLO
. PG2 is
tied to MR.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 (tied to MR) are
at logic low. Since MR is at logic low, RESET is also
at logic low. When EN1 is taken to logic low, V
OUT1
turns on. Later, when EN2 is taken to logic low, V
OUT2
turns on. When V
OUT1
reaches 95% of its regulated
output voltage, PG1 goes to logic high. When V
OUT2
reaches 95% of its regulated output voltage, PG2
(tied to MR) goes to logic high. When V
IN1
is greater
than V
UVLO
and M R (tied to PG2) is at logic high,
RESET is pulled to logic high after a 120ms delay.
When EN1 and EN2 are returned to logic high, both
devices power down and both PG1, PG2 (tied to
MR2), and RESET return to logic low.
Figure 34. Timing When V
OUT1
Is Enabled Before V
OUT2
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