Datasheet

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RESET
V
OUT2
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
V
I
V
OUT1
MR1
0.1 µF
10 µF
10 µF
0.1 µF
MR2
EN
TPS701xxPWP
(Fixed Output Option)
>2 V
<0.7 V
83%
95%
83%
95%
120ms
ENABLE
V
OUT2
V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQUENCE
NOTE A: t1 − Time at which both V
OUT1
and V
OUT2
are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
V
OUT2
faults out
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Application condition: MR2 is tied to PG1, V
IN1
and
V
IN2
are tied to same input voltage, the SEQ is tied to
logic high, the device is enabled, and V
OUT2
faults
out.
V
OUT2
begins to power up when the device is enabled
( EN is pulled low). When V
OUT2
reaches 83% of its
regulated voltage, V
OUT1
begins to power up. When
V
OUT1
reaches 95% of its regulated voltage, PG1
turns on and RESET switches to high voltage level
after a 120ms delay. When V
OUT2
faults out, V
OUT1
is
powered down because SEQ is high. PG1 is tied to
MR2 and both change state to logic low. RESET
goes low when V
OUT2
faults out (see Figure 44 ).
Figure 44. Timing when V
OUT2
Faults Out
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