Datasheet

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APPLICATION INFORMATION
Sequencing Timing Diagrams
V
OUT2
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
TPS701xxPWP
(Fixed Output Option)
V
I
V
OUT1
MR1
0.1 µF
RESET
10 µF
10 µF
0.1 µF
MR2
EN
>2 V
<0.7 V
250 kΩ
83%
95%
120ms
EN
V
OUT2
V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQ
95%
83%
NOTE A: t1 − Time at which both V
OUT1
and V
OUT2
are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
This section provides a number of timing diagrams
showing how this device functions in different con-
figurations.
Application condition: MR2 is tied to PG1, V
IN1
and
V
IN2
are tied to the same input voltage, the SEQ pin
is tied to logic low and the device is toggled with the
enable ( EN) function.
When the device is enabled ( EN is pulled low), V
OUT1
turns on first and V
OUT2
remains off until V
OUT1
reaches approximately 83% of its regulated output
voltage. At that time, V
OUT2
is turned on. When V
OUT1
reaches 95% of its regulated output, PG1 turns on
(active high). Since MR2 is connected to PG1 for this
application, it follows PG1. When V
OUT2
reaches 95%
of its regulated voltage, RESET switches to high
voltage level after a120ms delay (see Figure 40 ).
Figure 40. Timing when SEQ = Low
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