Low Dropout, DualĆOutput Linear Regulator EVM Using the TPS70151 User’s Guide April 2000 Mixed-Signal Products SLVU025A
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Preface About This Manual This user’s guide describes the TPS70151EVM–152 low dropout, dual-output evaluation module (SLVP152). The SLVP152 provides a convenient method for evaluating the performance of a dual-output linear regulator. How to Use This Manual - Chapter 1 Introduction Chapter 2 EVM Adjustments and Test Points Chapter 3 Circuit Design Chapter 4 Test Results Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement.
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Running Title—Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Low Dropout Voltage Linear Regulator Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Title—Attribute Reference Figures 1–1 1–2 1–3 1–4 1–5 2–1 3–1 3–2 3–3 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 Typical LDO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLVP152 EVM Universal LDO Tester Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction This user’s guide describes the TPS70151EVM–152 low dropout, dual-output evaluation module (SLVP152). LDOs provide ideal power supplies for rapidly transitioning DSP loads. The TPS701xx family of devices is designed to provide a complete power management solution for DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required.
Low Dropout Voltage Linear Regulator Circuit Operation 1.1 Low Dropout Voltage Linear Regulator Circuit Operation In TI’s low dropout voltage linear regulator topology, a PMOS transistor acts as the pass element. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading.
Design Strategy 1.2 Design Strategy The TI SLVP152 EVM provides a convenient method for evaluating the performance of TPS701xx dual-output linear regulators. The EVM provides proven, demonstrated reference designs and test modes to aid in evaluation. The board contains a power supply along with an onboard transient generator. The transient slew rate can be modified by changing two resistors. Jumpers allow settings of minimum/maximum load as well as device-enabling and power sequencing.
Schematic 1.3 Schematic Figure1–2 shows the SLVP152 EVM schematic diagram. Figure 1–2. SLVP152 EVM Universal LDO Tester Schematic Diagram TP16 R9 2 kΩ C2 C5 100 µF 0.
Bill of Materials 1.4 Bill of Materials Table 1–2 lists materials required for the SLVP152 EVM. Table 1–2. SLVP152 EVM Bill of Materials Ref Des Qty Part Number Description MFG Size C1 1 ECJ-2VF1C105Z Capacitor, ceramic, 1.0 uF, 16 V, 80% – 20%, Y5V Panasonic 805 C4 – 7, 9, 7 14, 15 GRM39X7R104K016A Capacitor, ceramic, 0.
Bill of Materials Table 1–2. SLVP152 EVM Bill of Materials (Continued) Ref Des Qty Part Number Description MFG Size S1 1 EG1218 Switch, 1P2T, slide, PC-mount E–Switch 0.1” TP1, 2, 16, 17 4 131–4244–00 Adaptor, 3.5-mm probe clip (or 131–5031–00) Tektronix TP3 – 15 13 240–345 Test point, red Farnell U1 1 TLC555D IC, timer TI SO8 U2 1 TPS2812D IC, MOSFET driver, dual buffer TI SO8 U3 1 TPS70151PWP IC, LDO regulator, dual-output TI PWP20 –– 1 SLVP152, Rev.
Board Layout 1.5 Board Layout Figures 1–3 through 1-5 show the board layout for the SLVP125 EVM. Figure 1–3. Top Layer Top Layer Figure 1–4.
Board Layout Figure 1–5.
Chapter 2 EVM Adjustments and Test Points This chapter explains the following EVM adjustment modes: - Adjustment by switch and jumper Adjustment through changing components Figure 2–1 shows the locations of the adjustment points on the board. Topic Page 2.1 Adjustment by Switch and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2.2 Adjustment Through Component Changes . . . . . . . . . . . . . . . . . . . . . . 2–3 2.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . .
Adjustment by Switch and Jumpers 2.1 Adjustment by Switch and Jumpers S1 switches the transient generator on or off. Table 2–1 lists adjustments that can be made by jumpers. Table 2–1. Jumper Functions Jumper Setting Functional Description JP1 Short 1-2 – MR2 tied to GND RESET follows MR2 Short 2-3 – MR2 tied to PG_1 RESET will go high after a 120 ms delay when VOUT2 reaches 95% of its regulated voltage and when PG_1 goes high due to VOUT1 reaching 95% of its regulated voltage.
Adjustment Through Component Changes 2.2 Adjustment Through Component Changes Through minor soldering work, the DUT can be changed to any of the fixedvoltage members of the TPS701xx LDO family. In addition, Table 2–2 summarizes the most common components which a user might wish to replace in order to more fully characterize the LDO. Table 2–2.
Test Setup 5) Verify that the output voltage (measured at the VOUT1 and VOUT2 pins respectively) has the desired value. 6) Table 2–4 shows the three recommended options for loading each regulator. Table 2–4.
Chapter 3 Circuit Design This chapter describes the LDO circuit design procedure. Topic Page 3.1 Temperature Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 3.2 ESR and Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Considerations 3.1 Temperature Considerations To protect the device and assure the specifications, the maximum junction temperature should not exceed 125°C. If the temperature exceeds 150°C, thermal shutdown will turn off the device. This restriction limits the power dissipation the regulator can handle in any given application.
ESR and Transient Response Figure 3–2 shows the output capacitor and its parasitic impedances in a typical LDO output stage. Figure 3–2. LDO Output Stage With Parasitic Resistances ESR IO LDO – VESR RESR + + VI RLOAD VO – CO In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into or out of the CO branch.
ESR and Transient Response Figure 3–3.
Chapter 4 Test Results This chapter presents laboratory test results for the TPS70151 LDO design. Topic 4.1 Page Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Results 4.1 Test Results Figures 4–1 through 4–9 show the results of various test conditions using the TPS70151 device. In figures 4–1 through 4–3, channel 1 is regulator 1 output voltage and channel 4 is the load current. In figures 4–4 through 4–9, channel 1 is regulator 1 output, channel 2 is regulator 2 output, and channel 4 is RESET. Channel 3 is PG_1 in figures 4–4 through 4–8. Channel 3 is MR1 in figure 4–9. Figure 4–1.
Test Results Figure 4–3. No Load – Full Load (500 mA) Transition With CO = 33 µF POSCAP – Maximum Transient Droop Voltage The maximum transient droop voltage is 56 mV. Figure 4–4. Timing When SEQUENCE = Low VIN1 = VIN2 at 5V and both VOUT1 (CH1) and VOUT2 (CH2) have no load. EN is pulsed with a fast pulse. VOUT1 powers up before VOUT2 when SEQUENCE = low. PG_1 (CH3), tied to MR1, goes high when VOUT1 reaches 95% of regulated voltage.
Test Results Figure 4–5. Timing When SEQUENCE = Low, Including RESET VIN1 = VIN2 at 5V and both VOUT1 (CH1) and VOUT2 (CH2) have no load. EN is pulsed with a fast pulse. VOUT1 powers up before VOUT2 when SEQUENCE = low. PG_1 (CH3), tied to MR1, goes high when VOUT1 reaches 95% of regulated voltage. After a 120 ms delay, RESET (CH4) is being driven by both VOUT1 and VOUT2 power good. Figure 4–6. Timing When SEQUENCE = High VIN1 = VIN2 at 5V and both VOUT1 (CH1) and VOUT2 (CH2) have no load.
Test Results Figure 4–7. Timing When SEQUENCE = High and VOUT1 Faults Out When SEQUENCE = high, VOUT2 (CH2) remains on even after VOUT1 (CH1) faults out due to current limit. The VOUT1 fault causes PG_1 (CH3), tied to MR1, to go low. MR1 causes RESET (CH4) to go low. Figure 4–8. Timing When SEQUENCE = High and VOUT2 Faults Out When SEQUENCE = high and VOUT2 (CH2) faults out due to current limit, VOUT1 (CH1) is disabled and PG_1 (CH3), tied to MR1, goes low. The VOUT2 fault causes RESET (CH4) to go low.
Test Results Figure 4–9. Timing When MR Is Toggled MR1 (CH3)is taken low and RESET (CH4) follows MR1. VOUT1 (CH1) and VOUT2 (CH2) are unaffected. All results are consistent with those reported in the SLVS222 datasheet.
