Datasheet

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DEVICE INFORMATION
UVLO
Thermal
Shutdown
Shutdown
V_UVLO
+−
Current
Sense
Reference
V
ref
V
ref
ENA_1
ENA_
1
10 kΩ
Rising Edge
Deglitch
0.95 × V
ref
FB2
Falling Edge
Delay
V
IN1
PG1 Comp
0.95 × V
ref
FB1
Rising Edge
Deglitch
Falling Edge
Deglitch
0.83 × V
ref
FB2
UV Comp
Falling Edge
Deglitch
0.83 × V
ref
FB1
UV Comp
Power
Sequence
Logic
ENA_1
ENA_2
V
CC
Current
Sense
+−
10 kΩ
ENA_2
ENA_2
FB2
V
ref
V
IN1
(2 Pins)
GND
EN
SEQ
(see Note B)
V
IN2
(2 Pins)
V
OUT1
(2 Pins)
V
SENSE1
(see Note
A)
PG1
MR2
RESET
MR1
V
SENSE2
(see Note
A)
V
OUT2
(2 Pins)
FB1
V
IN1
Shutdown
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating junction temperature range (T
J
= -40 ° C to +125 ° C), V
IN1
or V
IN2
= V
OUT(nom)
+ 1V, I
O
= 1mA,
EN = 0, C
O
= 33µF, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dropout voltage
(4)
I
O
= 500mA, T
J
= 25 ° C V
IN1
= 3.2V 170 mV
Dropout voltage
(4)
I
O
= 500mA, V
IN1
= 3.2V 275 mV
Peak output current
(4)
2ms pulse width 750 mA
Discharge transistor current V
OUT1
= 1.5V 7.5 mA
UVLO threshold 2.4 2.65 V
FB Terminal
Input current: TPS70102 FB = 1.8V 1 µA
(4) Input voltage (V
IN1
or V
IN2
) = V
O(typ)
- 100mV. For 1.5V, 1.8V and 2.5V regulators, the dropout voltage is limited by input voltage range.
The 3.3V regulator input is set to 3.2V to perform this test.
Fixed Voltage Version
A. For most applications, V
SENSE1
and V
SENSE2
should be externally connected to V
OUT
as close as possible to the
device. For other implementations, refer to SENSE terminal connection discussion in the Application Information
section.
B. If the SEQ terminal is floating at the input, V
OUT2
powers up first.
6