Datasheet

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LDO
V
in
V
ESR
I
out
R
ESR
C
out
R
LOAD
V
out
+
−
ESR 1
ESR 2
ESR 3
3
1
2
t
1
t
2
I
O
V
O
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Figure 48. LDO Output Stage with Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V
(CO)
= V
OUT
). This means no current is flowing into the C
O
branch. If I
OUT
suddenly increases (a transient condition), the following occurs:
• The LDO is not able to supply the sudden current need due to its response time (t
1
in Figure 45). Therefore,
capacitor C
O
provides the current for the new load condition (dashed arrow). C
O
now acts like a battery with
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop occurs at R
ESR
.
This voltage is shown as V
ESR
in Figure 44.
• When C
O
is conducting current to the load, initial voltage at the load will be V
O
= V
(CO)
– V
ESR
. Due to the
discharge of C
O
, the output voltage V
O
drops continuously until the response time t
1
of the LDO is reached
and the LDO resumes supplying the load. From this point, the output voltage starts rising again until it
reaches the regulated voltage. This period is shown as t
2
in Figure 49 .
Figure 49. Correlation of Different ESRs and Their Influence on the Regulation of V
O
at a Load Step from
Low-to-High Output Current
29