Datasheet

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1.8 V
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
TPS70151 PWP
5 V
3.3 V
I/O
MR1
Core
0.1 µF
RESET
10 µF
10 µF
0.1 µF
DSP
MR2
PG1
EN
250 kΩ
>2 V
<0.7 V
250 kΩ
>2 V
<0.7 V
>2 V
<0.7 V
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on
regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a
voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA
over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN
(enable) shuts down both regulators, reducing the input current to 1µA at T
J
= 25 ° C.
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two
regulators are sensed at the V
SENSE1
and V
SENSE2
pins, respectively.
The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is
enabled and the SEQ terminal is pulled high or left open, V
OUT2
turns on first and V
OUT1
remains off until V
OUT2
reaches approximately 83% of its regulated output voltage. At that time V
OUT1
is turned on. If V
OUT2
is pulled
below 83% (for example, an overload condition), V
OUT1
is turned off. Pulling the SEQ terminal low reverses the
power-up order and V
OUT1
is turned on first. The SEQ pin is connected to an internal pull-up current source.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage conditions at V
OUT1
, which can be used to implement an SVS for the circuitry
supplied by regulator 1.
The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP
systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of
V
OUT2
and both manual reset pins ( MR1 and MR2). When V
OUT2
reaches 95% of its regulated voltage and MR1
and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes
to the logic low state when the V
OUT2
regulated output voltage is pulled below 95% (for example, an overload
condition) of its regulated voltage. To monitor V
OUT1
, the PG1 output pin can be connected to MR1 or MR2.
The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning on
until V
IN1
reaches 2.5V.
2