Datasheet

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UVLO
Thermal
Shutdown
Shutdown
2.5 V
+−
Current
Sense
Reference
V
ref
V
ref
ENA_1
ENA_1
Rising Edge
Deglitch
0.95 × V
ref
FB2
Falling Edge
Delay
V
IN1
PG1 Comp
0.95 × V
ref
FB1
Rising Edge
Deglitch
Falling Edge
Deglitch
0.83 × V
ref
FB2
UV Comp
Falling Edge
Deglitch
0.83 × V
ref
FB1
UV Comp
Power
Sequence
Logic
Shutdown
ENA_1
ENA_2
V
CC
Current
Sense
+−
ENA_2
ENA_2
V
ref
V
IN1
(2 Pins)
GND
EN
SEQ
(see Note B)
V
IN2
(2 Pins)
V
OUT1
(2 Pins)
FB1
(see Note
A)
PG1
MR2
RESET
MR1
FB2
(see Note
A)
V
OUT2
(2 Pins)
V
IN1
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
DEVICE INFORMATION (continued)
Adjustable Voltage Version
A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the
device. For other implementations, refer to FB terminals connection discussion in the Application Information
section.
B. If the SEQ terminal is floating at the input, V
OUT2
powers up first
7