Datasheet

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RESET
V
OUT2
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
V
I
V
OUT1
MR1
0.1 µF
10 µF
10 µF
0.1 µF
MR2
EN
TPS701xxPWP
(Fixed Output Option)
>2 V
<0.7 V
250 kΩ
120ms
EN
V
OUT2
V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQUENCE
95%
83%
83%
95%
NOTE A: t1 − Time at which both V
OUT1
and V
OUT2
are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
V
OUT1
faults out
TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Application condition: MR2 is tied to PG1, V
IN1
and
V
IN2
are tied to the same input voltage, the SEQ pin
is tied to logic high and V
OUT1
faults out.
V
OUT2
begins to power up when the device is enabled
( EN is pulled low). When V
OUT2
reaches 83% of its
regulated voltage, then V
OUT1
begins to power up.
When V
OUT1
reaches 95% of its regulated voltage,
PG1 turns on and RESET switches to high voltage
level after a 120ms delay. When V
OUT1
faults out,
V
OUT2
remains powered on because the SEQ pin is
high. PG1 is tied to MR2 and both change state to
logic low. RESET is driven by MR2 and goes to logic
low when V
OUT1
faults out (see Figure 43 ).
Figure 43. Timing when V
OUT1
Faults Out
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