Datasheet

2.75V
1.8V
VMIC1/2.OUT
Digmic
bias(LDO)
VRIO=1.8V
DIG.MIC.CLK0/1
BUF
DIGMICleft
Audiodigitalfilter
Comparator
DIGMICright
Q
S
R
0.9V
DIG.MIC.0/1
Comparator
Audiodigitalfilter
Q
Q
Q
R
S
AudioPLL
DigialMIC
clockgenerator
50*Fs
50*Fs
032-035
TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
Figure 6-22. Digital Microphone Bias Module Block Diagram
Table 6-18 and Table 6-19 list the characteristics of the digital microphone bias module.
Table 6-18. Digital Microphone Bias Module Characteristics
Parameter Test Conditions Min Typ Max Unit
Bias voltage 1.8 V
Load current 10 mA
PSRR (from VBAT) 20 Hz to 6.6 kHz 60 dB
External capacitor 0.3 1 3.3 μF
ESR for capacitor At 100 kHz 0.02 0.6 Ω
Table 6-19. Digital Microphone Bias Module Characteristics (2)
Parameter Test Conditions Min Typ Max Unit
Comparator high threshold 0.5*VDD_IO 0.7*VDD_IO
Comparator low threshold 0.3*VDD_IO 0.5*VDD_IO
Startup time 2 μs
DIG.MIC.0 (t
HOLD
) from DIG.MIC.CLK0 edge 4 ns
DIG.MIC.1 (t
HOLD
) from DIG.MIC.CLK1 edge 4 ns
88 Audio/Voice Module Copyright © 2008–2011, Texas Instruments Incorporated
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