Datasheet

TPS65950
www.ti.com SWCS032E–OCTOBER 2008–REVISED JANUARY 2011
6-34 Voice Uplink Frequency Response With F
S
= 16 kHz (Frequency Range 6200 to 7000 Hz).......................... 97
7-1 USB 2.0 PHY Overview ......................................................................................................... 99
7-2 USB System Application Schematic.......................................................................................... 101
7-3 MCPC UART and Handshake Mode Data Flow............................................................................ 102
7-4 MCPC UART and Handshake Mode Timings............................................................................... 103
7-5 USB-CEA Carkit UART Data Flow ........................................................................................... 104
7-6 USB-CEA Carkit UART Timing Parameters................................................................................. 105
7-7 HS USB Interface—Transmit and Receive Modes (ULPI 8-Bit) .......................................................... 105
8-1 Typical Application Schematics ............................................................................................... 115
8-2 Typical Application Schematic (In-Rush Current Limitation) .............................................................. 116
8-3 Typical Application Schematic (BCI Not Used) ............................................................................. 117
8-4 Automatic Charge Sequence Timing Diagram.............................................................................. 124
9-1 Conversion Sequence General Timing Diagram ........................................................................... 128
10-1 LED Driver Block Diagram..................................................................................................... 129
11-1 Keyboard Connection .......................................................................................................... 130
12-1 Clock Overview ................................................................................................................. 131
12-2 HFCLKIN Clock Distribution................................................................................................... 133
12-3 Example of Wired-OR Clock Request........................................................................................ 135
12-4 HFCLKIN Squared Input Clock ............................................................................................... 135
12-5 32-kHz Oscillator Block Diagram In Master Mode With Crystal .......................................................... 136
12-6 32-kHz Crystal Input............................................................................................................ 137
12-7 32-kHz Oscillator Block Diagram Without Crystal Option 1 ............................................................... 139
12-8 32-kHz Oscillator Block Diagram Without Crystal Option 2 ............................................................... 139
12-9 32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3........................................... 139
12-10 32-kHz Square- or Sine-Wave Input Clock.................................................................................. 140
12-11 32.768-kHz Clock Output Block Diagram.................................................................................... 141
12-12 32KCLKOUT Output Clock .................................................................................................... 142
12-13 HFCLKOUT Output Clock ..................................................................................................... 142
12-14 32KCLKOUT and HFCLKOUT Clock Stabilization Time .................................................................. 143
12-15 HFCLKOUT Behavior ......................................................................................................... 143
13-1 I
2
C Interface—Transmit and Receive in Slave Mode ...................................................................... 145
13-2 I2S Interface—I2S Master Mode.............................................................................................. 147
13-3 I2S Interface—I2S Slave Mode ............................................................................................... 147
13-4 TDM Interface—TDM Master Mode .......................................................................................... 148
13-5 Voice/BT PCM Interface—Master Mode (Mode 1) ......................................................................... 150
13-6 Voice PCM Interface—Slave Mode (Mode 1)............................................................................... 150
13-7 JTAG Interface Timing ......................................................................................................... 152
14-1 Debouncing Sequence Chronogram Example.............................................................................. 154
16-1 Printed Device Reference ..................................................................................................... 160
16-2 TPS65950 Mechanical Package Top View.................................................................................. 161
16-3 Ball Size.......................................................................................................................... 161
Copyright © 2008–2011, Texas Instruments Incorporated List of Figures 7