Datasheet

030-022
PWRON
REGEN
VIO
VPLL1
VDD2
VDD1
32KCLKOUT
SYSEN
CLKEN
HFCLKOUT
NRESPWRON
4791 s – 3MHzoscillatorsetting+internalregm
1068 sforexternalsupplyrampm
1099 sforVDD2stabilizationm
1179 sforVIOdc-dcstablilizationm
1022 sm
1099 sforVDD2stabilizationm
61 sm
1175 sforVDD1stabilizationm
1953 sfordigitalclocksettingm
64 sm
1.8V
1.8V
1.2V
1.2V
TPS65950
www.ti.com SWCS032E–OCTOBER 2008–REVISED JANUARY 2011
4.5.3.4 Power On in Slave_C021_Generic Mode
Figure 4-11 describes the timing and control that must occur in the Slave_C021_Generic mode.
Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 4-8.
Figure 4-11. Timings—Power On in Slave_C021_Generic Model
4.5.4 Power-Off Sequence
This section describes the signal behavior required to power down the system.
4.5.4.1 Power-Off Sequence in Master Modes
Figure 4-12 shows the timing and control that occur during the power-off sequence in master modes.
Copyright © 2008–2011, Texas Instruments Incorporated Power Module 63
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