Datasheet

TPS65950
www.ti.com SWCS032E–OCTOBER 2008–REVISED JANUARY 2011
4.1.16 USB LDO Short-Circuit Protection Scheme
The short-circuit current for the LDOs and dc-dc converters in TPS65950 is approximately twice the
maximum load current. In certain cases when the output of the block is shorted to ground, the power
dissipation can exceed the 1.2-W requirement if no action is taken. A short-circuit protection scheme is
included in the TPS65950 to ensure that if the output of an LDO or dc-dc is short-circuited, the power
dissipation does not exceed the 1.2-W level.
The three USB LDOs, VRUSB3V1, VRUSB1V8, and VRUSB1V5, are included in this short-circuit
protection scheme, which monitors the LDO output voltage at a frequency of 1 Hz and generates an
interrupt (sc_it) when a short circuit is detected.
The scheme compares the LDO output voltage to a reference voltage and detects a short circuit if the
LDO voltage drops below this reference value (0.5 or 0.75 V programmable). In the case of the
VRUSB3V1 and VRUSB1V8 LDOs, the reference is compared with a divided-down voltage (1.5 V typical).
If a short circuit is detected on VRUSB3V1, the power subchip FSM switches this LDO to sleep mode.
If a short circuit is detected on VRUSB1V8 or VRUSB1V5, the power subchip FSM switches off the
relevant LDO.
4.2 Power References
The bandgap voltage reference is filtered (resistance/capacitance [RC] filter) using an external capacitor
connected across the VREF output and an analog ground (REFGND). The VREF voltage is scaled,
distributed, and buffered in the device. The bandgap is started in fast mode (not filtered), and is set
automatically by the D machine in slow mode (filtered, less noisy) when required.
Table 4-18 lists the characteristics of the voltage references.
Table 4-18. Voltage Reference Characteristics
Parameter Test Conditions Min Typ Max Unit
Output Load Condition
Filtering capacitor Connected from V
REF
to REFGND 0.3 1 2.7 μF
Electrical Characteristics
V
IN
Input voltage On mode 2.7 3.6 4.5 V
Internal bandgap reference voltage On mode, measured through TESTV terminal 1.272 1.285 1.298 V
Reference voltage (V
REF
terminal) On mode 0.725 0.75 0.7575 V
Retention mode reference On mode 0.492 0.5 0.508 V
I
REF
NMOS sink 0.9 1 1.1 µA
Ground current Bandgap 25 µA
IREF block 20
Preregulator 15
VREF buffer 10
Retention reference buffer 10
Output spot noise 100 Hz 1 µV/√Hz
A-weighted noise (rms) 200 nV (ms)
P-weighted noise (rms) 150 nV (ms)
Integrated noise 20 Hz to 100 kHz 2.2 µV
I
BIAS
trim bit LSB 0.1 µA
Ripple rejection < 1 MHz from VBAT 60 dB
Start-up time 1 ms
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