Datasheet

TPS65950
www.ti.com SWCS032E–OCTOBER 2008–REVISED JANUARY 2011
4.1.1 VDD1 dc-dc Regulator
4.1.1.1 VDD1 dc-dc Regulator Characteristics
The VDD1 dc-dc regulator is a stepdown dc-dc converter with a configurable output voltage. The
programming of the output voltage and the characteristics of the dc-dc converter are
SmartReflex-compatible. The regulator can be put in sleep mode to reduce its leakage (PFM) or
power-down mode when it is not being used. Table 4-3 lists the characteristics of the regulator.
Table 4-2. Part Names With Corresponding VDD1 Current Support
Device Name VDD1 Current Support
TPS65950A2ZXN/R (some bug fixes, see errata) 1.2 A
TPS65950A3ZXN/R (same as TPS65950A2 + 1 GHz support with higher current support) 1.4 A
Table 4-3. VDD1 dc-dc Regulator Characteristics
Parameter Comments Min Typ Max Unit
Input voltage range 2.7 3.6 4.5 V
Output voltage 0.6 1.45 V
Output voltage step Covering the 0.6 to 1.45-V range 12.5 mV
Output accuracy
(1)
0.6 to < 0.8 V –6% 6%
0.8 to 1.45 V –4% 4%
Switching frequency 3.2 MHz
I
O
= 10 mA, sleep 82%
Conversion efficiency
(2)
, Figure 4-2 in active and
100 mA < I
O
< 400 mA 85%
sleep modes
400 mA < I
O
< 600 mA 80%
600 mA < I
O
< 800 mA 75%
Active mode, Output Voltage 0.6 V to 1.45 V 1200 mA
for TPS65950A2/TPS65950A3
Output current Active mode, Output Voltage 1.2 V to1.45 V 1400 mA
for TPS65950A3
Sleep mode 10 mA
Ground current (I
Q
) Off at 30°C 3 μA
Sleep, unloaded 30 50
Active, unloaded, not switching 300
Short-circuit current V
IN
= V
Max
2.2 A
Load regulation 0 < I
O
< I
Max
20 mV
I
O
= 10 mA to 600 +10 mA,
Transient load regulation
(3)
–65 50 mV
Maximum slew rate is 600mA/100 ns.
Line regulation 10 mV
Transient line regulation 300 mV
PP
ac input, 10-μs rise and fall time 10 mV
Startup time 0.25 1 ms
Recovery time From sleep mode to on mode with constant <10 100 μs
load
Slew rate (rising or falling)
(4)
4 8 16 mV/μs
Output shunt resistor (pulldown) 500 700 Ω
(1) Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process). Under current load
condition step: 600 mA in 100 ns with a ±20% external capacitor accuracy or 400 mA in 100 ns with a ±50% external capacitor accuracy
(2) VBAT = 3.6 V, VDD1 = 1.2 V, Fs = 3.2 MHz, L = 1 μH, L
DCR
= 100 mΩ, C = 10 μF, ESR = 10 mΩ
(3) For negative transient load, the output voltage must discharge completely and settle to its final value within 100 ms.
Transient load is specified at Vout max with a ±50% external capacitor accuracy and includes temperature and process variation.
(4) Load current varies proportionally with the output voltage. The slew rate is for increasing and decreasing voltages and the maximum
load current is 1.1 A.
Copyright © 2008–2011, Texas Instruments Incorporated Power Module 35
Submit Documentation Feedback
Product Folder Link(s): TPS65950