Datasheet

TPS65950
www.ti.com SWCS032E–OCTOBER 2008–REVISED JANUARY 2011
Table 3-4. Digital I/O Electrical Characteristics
VOL (V) VOH (V) VIL (V) VIH (V)
Max Freq Load (pF) Rise
Pin Name Fall Time (ns)
(MHz) Output Mode Time (ns)
Min Max Min Max Min Max Min Max
GPIO0/CD1
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2
JTAG.TDO
GPIO0/CD2
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2
JTAG.TMS
GPIO2
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
Test1
GPIO15
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
Test2
GPIO16
PWM0 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
Test3
GPIO17
VIBRA.SYNC
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
PWM1
Test4
START.ADC 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6 16.7 16.7
SYSEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 5.2 5.2
CLKEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
CLKEN2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
CLKREQ 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
INT1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
INT2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
NRESPWRON 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
NRESWARM 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
PWRON 0 0.35×1.8V 0.65×1.8V VBAT 3 33.3 33.3
NSLEEP1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
NSLEEP2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
CLK256FS 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 12.288 30 16.3 16.3
VMODE1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
BOOT0 0 RL 3 33.3 33.3
BOOT1 0 RL 3 33.3 33.3
REGEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
MSECURE 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
I2C.SR.SDA 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 Up to 400
VMODE2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.4 29.4 29.4
I2C.SR.SCL 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 10.0 10.0
I2C.CNTL.SDA 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 Up to 400
I2C.CNTL.SCL 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 10.0 10.0
PCM.VCK 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 33.0
PCM.VDR 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 100.0
PCM.VDX 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 33.0
PCM.VFS 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 33.0 33.0
I2S.CLK 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6.5 30 33.0 33.0
I2S.SYNC 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6.5 30 33.0 33.0
I2S.DIN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.25 30 33.0 33.0
I2S.DOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.25 30 29.0 29.0
UART1.TXD 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.0 33.0
GPIO8
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0
UART1.RXD
RTSO/CLD64K.OUT/
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.0 33.0
BERCLK.OUT
CTSI/BERDATA.OUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.0 33.0
MANU 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0
32KCLKOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.032 30 16 16
HFCLKOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 38.4 30 2.6 2.6
Copyright © 2008–2011, Texas Instruments Incorporated Electrical Characteristics 29
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