Datasheet

TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
Table 2-1. Ball Characteristics (continued)
PU[6] (kΩ) PD[6] (kΩ) Buffer
Pin A/D Reference Level
Ball[1] Type[4] Strength
Name[2] [3] RL[5]
Min[7] Typ[8] Max[9] Min Typ Max
(mA)[10]
GPIO7 D I/O IO_1P8 2
VIBRA.SYNC D I IO_1P8
N14 75 100 202 59 100 144
PWM1 D O IO_1P8 4
Test4 D I/O IO_1P8 2
J9 START.ADC D I IO_1P8
C13 SYSEN D OD/I IO_1P8 4.7 7.35 10 2
C6 CLKEN D O IO_1P8 2
D7 CLKEN2 D O IO_1P8 2
G10 CLKREQ D I IO_1P8 60 100 146
F10 INT1 D O IO_1P8 2
F9 INT2 D O IO_1P8 2
A13 NRESPWRON D O IO_1P8 2
B13 NRESWARM D I IO_1P8 2
A11 PWRON D I VBAT
B14 NC
P7 NSLEEP1 D I IO_1P8
G9 NSLEEP2 D I IO_1P8
D13 CLK256FS
(1)
D O IO_1P8 2
F8 VMODE1 D I IO_1P8
K11 BOOT0 A/D I/O VBAT
J11 BOOT1 A/D I/O VBAT
A10 REGEN D OD VBAT 5.5 8 12 2
H8 MSECURE D I IO_1P8
N16 VREF A Power VREF
N15 AGND A Power GND GND
NC
C4
I2C.SR.SDA D I/O IO_1P8 2.5 3.4 12
VMODE2 D I IO_1P8 2
D6
I2C.SR.SCL D I/O IO_1P8 2.5 3.4 12
D4 I2C.CNTL.SDA D I/O IO_1P8 2.5 3.4 12
D5 I2C.CNTL.SCL D I IO_1P8 2.5 3.4 12
R1 PCM.VCK D I/O IO_1P8 2
T2 PCM.VDR D I/O IO_1P8 2
T15 PCM.VDX D I/O IO_1P8 2
R16 PCM.VFS D I/O IO_1P8 2
L3 I2S.CLK D I/O IO_1P8 2
K6 I2S.SYNC D I/O IO_1P8 2
K4 I2S.DIN D I IO_1P8 2
K3 I2S.DOUT D O IO_1P8 2
E2 MIC.MAIN.P A I MICBIAS1.OUT
F2 MIC.MAIN.M A I MICBIAS1.OUT
MIC.SUB.P A I MICBIAS2.OUT
G2
DIG.MIC.0 A I VMIC1.OUT
MIC.SUB.M A I MICBIAS2.OUT
H2
DIG.MIC.1 A I VMIC2.OUT
E3 HSMIC.P A I VINTANA2.OUT
F3 HSMIC.M A I VINTANA2.OUT
D10 VBAT.LEFT A Power VBAT
D9 VBAT.LEFT A Power VBAT
B9 IHF.LEFT.P A O VBAT
B10 IHF.LEFT.M A O VBAT
C10 GND.LEFT A Power GND GND
C9 GND.LEFT A Power GND GND
D12 VBAT.RIGHT A Power VBAT
(1) To avoid reflection on this pin caused by impedance mismatch, a serial resistance (Rs) of 33 Ω must be added.
16 Terminal Description Copyright © 2008–2011, Texas Instruments Incorporated
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