Datasheet

I2S.SYNC
I2S.CLK
I2S.DIN
I2S.DOUT
23
22 1
0 23
22
1
0 23
22 1
0 23
22 1
0
23
22
1
0
23
22 1
0 23
22 1
0 23
22 1
0
Channel1 Channel2 Channel3 Channel4
T1
T3 T3 T3 T3 T3 T3 T3 T3
T4 T4 T4 T4 T4 T4 T4 T4
T5 T5 T5 T5 T5 T5 T5 T5
T2 T2 T2 T2
T0 T1
8dummy
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8dummy
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8dummy
bits
8dummy
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8dummy
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032-080
TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
Table 13-5. I2S Interface—Timing Requirements (continued)
Notation Parameter Min Max Unit
I3 t
su(DIN-CLKH)
Setup time, I2S.DIN valid to I2S.CLK high 5 ns
I4 t
h(DIN-CLKH)
Hold time, I2S.DIN valid from I2S.CLK high. 5 ns
I6 t
su(SYNC-CLKH)
Setup time, I2S.SYNC valid to I2S.CLK high 5 ns
I7 t
h(SYNC-CLKH)
Hold time, I2S.SYNC valid from I2S.CLK high 5 ns
The capacitive load for Table 13-6 is 7 pF.
Table 13-6. I2S Interface—Switching Characteristics
Notation Parameter Min Max Unit
Master Mode
I0 t
c(CLK)
Cycle time, I2S.CLK
(1)
1/64 * Fs ns
I1 t
w(CLK)
Pulse duration, I2S.CLK high or low
(2)
0.45 * P 0.55 * P ns
I2 t
d(CLKL-SYNC)
Delay time, I2S.CLK falling edge to I2S.SYNC transition –10 10 ns
I5 t
d(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT transition –10 10 ns
Slave Mode
I5 t
d(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT transition 0 20 ns
(1) Fs = 8 to 48 kHz; 96 kHz for RX path only
(2) P = I2S.CLK period
13.4.2 TDM Data Format
Table 13-7 and Table 13-8 assume testing over the recommended operating conditions (see Figure 13-4).
Figure 13-4. TDM Interface—TDM Master Mode
The timing requirements in Table 13-7 are valid on the following conditions of input slew and output load:
• Rise and fall time range of inputs (SYNC, DIN) is t
R
/t
F
= 1.0 ns/6.5 ns
• Capacitance load range of outputs (CLK, SYNC, DOUT) is C
Load
= 1 pF/30 pF
Table 13-7 lists the master mode timing requirements for the TDM interface.
Table 13-7. TDM Interface Master Mode Timing Requirements
Notation Parameter Min Max Unit
T3 t
su(DIN-CLKH)
Setup time, TDM.DIN valid to TDM.CLK high 25 ns
T4 t
h(DIN-CLKH)
Hold time, TDM.DIN valid from TDM.CLK high 0 ns
148 Timing Requirements and Switching Characteristics Copyright © 2008–2011, Texas Instruments Incorporated
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