Datasheet

I2S.SYNC
I2S.CLK
I2S.DIN
I2S.DOUT
23
22 1
0
8dummybits
23
22 1
0
8dummybits
23
22
23
22 1
0
8dummybits
23
22
1
0
8dummybits
23
22
Leftchannel
Rightchannel
I2 I2 I2
I3 I3 I3
I3
I4 I4
I4
I4
I5
I5
I5 I5
I0 I1
I1
032-078
I2S.SYNC
I2S.CLK
I2S.DIN
I2S.DOUT
23
22 1
0
8dummybits
23
22
1
0
8dummybits
23
22
23
22 1
0
8dummybits
23
22 1
0
8dummybits
23
22
Leftchannel Rightchannel
I3 I3 I3 I3
I4 I4 I4 I4
I5 I5 I5 I5
I6 I7 I6I0 I1
I1
032-079
TPS65950
www.ti.com SWCS032E–OCTOBER 2008–REVISED JANUARY 2011
Figure 13-2. I2S Interface—I2S Master Mode
Figure 13-3. I2S Interface—I2S Slave Mode
The timing requirements in Table 13-5 are valid on the following conditions of input slew and output load:
• Rise and fall time range of inputs (SYNC, DIN) is t
R
/t
F
= 1.0 ns/6.5 ns
• Capacitance load range of outputs (CLK, SYNC, DOUT) is C
Load
= 1 pF/30 pF
The input timing requirements in Table 13-5 are given by considering a rising or falling time of 6.5 ns.
Table 13-5. I2S Interface—Timing Requirements
Notation Parameter Min Max Unit
Master Mode
I3 t
su(DIN-CLKH)
Setup time, I2S.DIN valid to I2S.CLK high2 25 ns
I4 t
h(DIN-CLKH)
Hold time, I2S.DIN valid from I2S.CLK high. 0 ns
Slave Mode
I0 t
c(CLK)
Cycle time, I2S.CLK
(1)
1/64 * Fs ns
I1 t
w(CLK)
Pulse duration, I2S.CLK high or low
(2)
0.45 * P 0.55 * P ns
(1) Fs = 8 to 48 kHz; 96 kHz for RX path only
(2) P = I2S.CLK period
Copyright © 2008–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 147
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