Datasheet

TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
Table 13-3. I
2
C Interface Timing Requirements (continued)
Notation Parameter Min Max Unit
Slave Standard Mode
I3 t
su(SDA-SCLH)
Setup time, SDA valid to SCL high 250 ns
I4 t
h(SCLL-SDA)
Hold time, SDA valid from SCL low 0 ns
I7 t
su(SCLH-SDAL)
Setup time, SCL high to SDA low 4.7 ns
I8 t
h(SDAL-SCLL)
Hold time, SCL low from SDA low 4 ns
I9 t
su(SDAH-SCLH)
Setup time, SDA high to SCL high 4 ns
Table 13-4. I
2
C Interface Switching Requirements
(1) (2)
Notation Parameter Min Max Unit
Slave HS Mode
I1 t
w(SCLL)
Pulse duration, SCL low 160 ns
I2 t
w(SCLH)
Pulse duration, SCL high 60 ns
Slave Fast-Speed Mode
I1 t
w(SCLL)
Pulse duration, SCL low 1.3
(3)
µs
I2 t
w(SCLH)
Pulse duration, SCL high 0.6 µs
Slave Standard Mode
I1 t
w(SCLL)
Pulse duration, SCL low 4.7 µs
I2 t
w(SCLH)
Pulse duration, SCL high 4 µs
(1) The capacitive load is:
100 pF in HS mode (3.4 Mbps)
400 pF in fast-speed mode (400 Kbps)
400 pF in standard mode (100 Kbps)
(2) SDA equals I2C.SR.SDA or I2C.CNTL.SDA
SCL equals I2C.SR.SCL or I2C.CNTL.SCL
(3) SCL low timing for slave fast-speed mode is compatibile with 0.79 µs.
13.4 Audio Interface: TDM/I2S Protocol
The TPS65950 acts as a master for the TDM and I2S interface or as a slave only for the I2S interface. If
the TPS65950 is the master, it must provide frame synchronization (TDM/I2S_SYNC) and bit clock
(TDM/I2S_CLK) to the host processor. If the TPS65950 is the slave, it receives frame synchronization and
bit clock.
The TPS65950 supports the I2S, TDM, left-justified, and right-justified data formats, but does not support
TDM slave mode.
13.4.1 I2S Right- and Left-Justified Data Format
Table 13-5 and Table 13-6 assume testing over the recommended operating conditions (see Figure 13-2
and Figure 13-3).
146 Timing Requirements and Switching Characteristics Copyright © 2008–2011, Texas Instruments Incorporated
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